From: "Gautham R. Shenoy" <gautham.shenoy@amd.com>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: Perry Yuan <perry.yuan@amd.com>,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Subject: Re: [PATCH v2 13/16] cpufreq/amd-pstate: Check if CPPC request has changed before writing to the MSR or shared memory
Date: Mon, 9 Dec 2024 14:26:14 +0530 [thread overview]
Message-ID: <Z1awrnPHwTVMht4E@BLRRASHENOY1.amd.com> (raw)
In-Reply-To: <20241208063031.3113-14-mario.limonciello@amd.com>
Hello Mario,
On Sun, Dec 08, 2024 at 12:30:28AM -0600, Mario Limonciello wrote:
> Move the common MSR field formatting code to msr_update_perf() from
> its callers.
>
> Ensure that the MSR write is necessary before flushing a write out.
> Also drop the comparison from the passive flow tracing.
>
> Reviewed-and-tested-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
[..snip..]
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index dd11ba6c00cc3..2178931fbf87b 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -224,15 +224,26 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata)
> static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
> u32 des_perf, u32 max_perf, u32 epp, bool fast_switch)
> {
> - u64 value;
> + u64 value, prev;
> +
> + value = prev = READ_ONCE(cpudata->cppc_req_cached);
> +
> + value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
> + AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
> + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf);
> + value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf);
> + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf);
> + value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
> +
> + if (value == prev)
> + return 0;
>
> - value = READ_ONCE(cpudata->cppc_req_cached);
> if (fast_switch) {
> - wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
> + wrmsrl(MSR_AMD_CPPC_REQ, value);
> return 0;
> } else {
> - int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> - READ_ONCE(cpudata->cppc_req_cached));
> + int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> +
> if (ret)
> return ret;
Ok, so you are recomputing the value in this patch. Does it also make
sense to move trace_amd_pstate_perf() call to this place?
--
Thanks and Regards
gautham.
> }
> @@ -528,9 +539,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
> {
> unsigned long max_freq;
> struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu);
> - u64 prev = READ_ONCE(cpudata->cppc_req_cached);
> u32 nominal_perf = READ_ONCE(cpudata->nominal_perf);
> - u64 value = prev;
>
> des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
>
> @@ -546,27 +555,14 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
> if (!cpudata->boost_supported)
> max_perf = min_t(unsigned long, nominal_perf, max_perf);
>
> - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
> - AMD_CPPC_DES_PERF_MASK);
> - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf);
> - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf);
> - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf);
> -
> if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
> trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
> cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc,
> - cpudata->cpu, (value != prev), fast_switch);
> + cpudata->cpu, fast_switch);
> }
>
> - if (value == prev)
> - goto cpufreq_policy_put;
> -
> - WRITE_ONCE(cpudata->cppc_req_cached, value);
> -
> amd_pstate_update_perf(cpudata, min_perf, des_perf, max_perf, 0, fast_switch);
>
> -cpufreq_policy_put:
> -
> cpufreq_cpu_put(policy);
> }
>
> @@ -1562,19 +1558,10 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
> static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
> {
> struct amd_cpudata *cpudata = policy->driver_data;
> - u64 value;
> u32 epp;
>
> amd_pstate_update_min_max_limit(policy);
>
> - value = READ_ONCE(cpudata->cppc_req_cached);
> -
> - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
> - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
> - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf);
> - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0);
> - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf);
> -
> if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
> epp = 0;
> else
> --
> 2.43.0
>
next prev parent reply other threads:[~2024-12-09 8:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-08 6:30 [PATCH v2 00/16] amd-pstate fixes and improvements for 6.14 Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 01/16] cpufreq/amd-pstate: Store the boost numerator as highest perf again Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 02/16] cpufreq/amd-pstate: Use boost numerator for upper bound of frequencies Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 03/16] cpufreq/amd-pstate: Add trace event for EPP perf updates Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 04/16] cpufreq/amd-pstate: convert mutex use to guard() Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 05/16] cpufreq/amd-pstate: Drop cached epp_policy variable Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 06/16] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 07/16] cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 08/16] cpufreq/amd-pstate: store all values in cpudata struct in khz Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 09/16] cpufreq/amd-pstate: Change amd_pstate_update_perf() to return an int Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 10/16] cpufreq/amd-pstate: Move limit updating code Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 11/16] cpufreq/amd-pstate: Cache EPP value and use that everywhere Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 12/16] cpufreq/amd-pstate: Always write EPP value when updating perf Mario Limonciello
2024-12-09 8:42 ` Gautham R. Shenoy
2024-12-09 16:49 ` Mario Limonciello
2024-12-09 17:15 ` Mario Limonciello
2024-12-10 11:10 ` Gautham R. Shenoy
2024-12-08 6:30 ` [PATCH v2 13/16] cpufreq/amd-pstate: Check if CPPC request has changed before writing to the MSR or shared memory Mario Limonciello
2024-12-09 8:56 ` Gautham R. Shenoy [this message]
2024-12-09 16:41 ` Mario Limonciello
2024-12-08 6:30 ` [PATCH v2 14/16] cpufreq/amd-pstate: Drop ret variable from amd_pstate_set_energy_pref_index() Mario Limonciello
2024-12-09 9:25 ` Gautham R. Shenoy
2024-12-08 6:30 ` [PATCH v2 15/16] cpufreq/amd-pstate: Set different default EPP policy for Epyc and Ryzen Mario Limonciello
2024-12-09 9:27 ` Gautham R. Shenoy
2024-12-08 6:30 ` [PATCH v2 16/16] cpufreq/amd-pstate: Drop boost_state variable Mario Limonciello
2024-12-09 10:24 ` Gautham R. Shenoy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z1awrnPHwTVMht4E@BLRRASHENOY1.amd.com \
--to=gautham.shenoy@amd.com \
--cc=Dhananjay.Ugwekar@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mario.limonciello@amd.com \
--cc=perry.yuan@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox