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with SMTP id 5b1f17b1804b1-43668b78c11mr157293045e9.28.1735224271050; Thu, 26 Dec 2024 06:44:31 -0800 (PST) Received: from linaro.org ([82.76.168.176]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436611ea47asm234453595e9.4.2024.12.26.06.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2024 06:44:30 -0800 (PST) Date: Thu, 26 Dec 2024 16:44:28 +0200 From: Abel Vesa To: "Peng Fan (OSS)" Cc: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Pengfei Li , "open list:NXP i.MX CLOCK DRIVERS" , "open list:NXP i.MX CLOCK DRIVERS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , open list Subject: Re: [PATCH V2] clk: imx: Apply some clks only for i.MX93 Message-ID: References: <20241225001443.883131-1-peng.fan@oss.nxp.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241225001443.883131-1-peng.fan@oss.nxp.com> On 24-12-25 08:14:43, Peng Fan (OSS) wrote: > From: Peng Fan > > Enable the LVDS gate, MIPI DSI, PXP, FLEXIO and MU only for i.MX93, > because i.MX91 does not support them. > > Update enet clk entry format to align with others. > > Fixes: a27bfff88dd2 ("clk: imx: add i.MX91 clk") > Signed-off-by: Peng Fan Reviewed-by: Abel Vesa > --- > > V2: > Update subject and commit log after phasing out more clks > https://lore.kernel.org/lkml/20241203130530.1206526-1-peng.fan@oss.nxp.com/ > > drivers/clk/imx/clk-imx93.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c > index 58a516dd385b..5bdd2bdce46e 100644 > --- a/drivers/clk/imx/clk-imx93.c > +++ b/drivers/clk/imx/clk-imx93.c > @@ -70,8 +70,8 @@ static const struct imx93_clk_root { > { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, > { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, > { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, > - { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, > - { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, > + { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, > + { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, > { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, > { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, > { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, > @@ -177,10 +177,10 @@ static const struct imx93_clk_ccgr { > { IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, }, > { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, > { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, > - { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED }, > - { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED }, > - { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub }, > - { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, > + { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 }, > + { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 }, > + { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub, PLAT_IMX93 }, > + { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub, PLAT_IMX93 }, > { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, > { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, > { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, > @@ -188,8 +188,8 @@ static const struct imx93_clk_ccgr { > { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, > { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, > { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, > - { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, > - { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, > + { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, 0, NULL, PLAT_IMX93}, > + { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, 0, NULL, PLAT_IMX93}, > { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, > { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, > { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, > @@ -238,10 +238,10 @@ static const struct imx93_clk_ccgr { > { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, 0, &share_count_sai3}, > { IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3}, > { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, > - { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, > - { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, > + { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, 0, NULL, PLAT_IMX93 }, > + { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, 0, NULL, PLAT_IMX93 }, > { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, > - { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, > + { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, 0, NULL, PLAT_IMX93 }, > { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, > { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, }, > { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, > @@ -256,8 +256,8 @@ static const struct imx93_clk_ccgr { > { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, > { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, }, > { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, }, > - { IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, }, > - { IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, }, > + { IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, }, > + { IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, }, > /* Critical because clk accessed during CPU idle */ > { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL}, > { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, > -- > 2.37.1 >