From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C510C3A8CB for ; Sun, 29 Dec 2024 09:03:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735463021; cv=none; b=uy5UGF9hZSkrZwSQYLgiA1COS/bopge/yFNsY4OYWhZ0U+tL8dN2JvY6+XTcOAELpc6YkPl/D3c8jiIF0L9rwNfcG6B2aZZu7PGBS4MUXYgb47fn+NVvRbMwZoVFeJvxH7x/voTBYxMlzArlpoOLi0Fttj+8Uf/oh/oyjJZIAPo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735463021; c=relaxed/simple; bh=zno3ESfN7d+kxJKfJK4yvuQUUXZubDSvb9qJC7KMr78=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=udcIO6rce8dHf8nJ3WJ1hdAQmf7AcbyxeJdMblJeKezGhRle01l+HndrfojLyPuwep1YAY7vLHR7R6tLmmy3rAn1MfekNChaOQKNP3e2Vl73PbHAMJG4OB8u1bWed7s1quRb1dBJDQx/pW5v9bBqXB3A3yx6PMAyDEDorBQB8DI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s46tNwKX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s46tNwKX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7171C4CED1; Sun, 29 Dec 2024 09:03:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1735463021; bh=zno3ESfN7d+kxJKfJK4yvuQUUXZubDSvb9qJC7KMr78=; h=Date:From:To:Cc:Subject:From; b=s46tNwKXYV3HWPS2k5n593/g+qPkh+/1KqvzEy7k/O3gU2kOUq6+t0zNmaiS5Mygd Ucxc/UOaRMdKANtR/S6xHczn4KmhQ6b4As8llK+Gyi4YvPwhB4VRtUxXJeR42zgwO8 Ag5/qTryz6+GzcOf1JNVn1JUcDhAUi595zRgboAvaqdtnmeaZ6NqSnvKfCtFG1qvag Mmd2zYCzdDGkw+hwBQnjWwnR4ZCu5xRiQmJW1vHKlPMLdUNT/SGdwMbklukVJgLILj lj5D/JcwcVTLAdrilixOFmg/OYghie/G0ku0SWsZxKIqISr0dnW72fPwf2vP2QzSFr XD7O44VlGHrmg== Date: Sun, 29 Dec 2024 10:03:36 +0100 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Arnaldo Carvalho de Melo , Jiri Olsa , Alexander Shishkin , Mark Rutland , Namhyung Kim , Andrew Morton , Kan Liang Subject: [GIT PULL] perf fixes Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Linus, Please pull the latest perf/urgent Git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2024-12-29 # HEAD: aa5d2ca7c179c40669edb5e96d931bf9828dea3d perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC Miscelaneous fixes: - Fix Intel Lunar Lake build-in event definitions - Fall back to (compatible) legacy features on new Intel PEBS format v6 hardware - Enable uncore support on Intel Clearwater Forest CPUs, which is the same as the existing Sierra Forest uncore driver. Thanks, Ingo ------------------> Kan Liang (3): perf/x86/intel/uncore: Add Clearwater Forest support perf/x86/intel/ds: Add PEBS format 6 perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC arch/x86/events/intel/core.c | 12 +++++++++++- arch/x86/events/intel/ds.c | 1 + arch/x86/events/intel/uncore.c | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 2e1e26846050..99c590da0ae2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -429,6 +429,16 @@ static struct event_constraint intel_lnc_event_constraints[] = { EVENT_CONSTRAINT_END }; +static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { + INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), + INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), + INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), + EVENT_EXTRA_END +}; EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); @@ -6422,7 +6432,7 @@ static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) intel_pmu_init_glc(pmu); hybrid(pmu, event_constraints) = intel_lnc_event_constraints; hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; - hybrid(pmu, extra_regs) = intel_rwc_extra_regs; + hybrid(pmu, extra_regs) = intel_lnc_extra_regs; } static __always_inline void intel_pmu_init_skt(struct pmu *pmu) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 1a4b326ca2ce..6ba6549f26fa 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2517,6 +2517,7 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; break; + case 6: case 5: x86_pmu.pebs_ept = 1; fallthrough; diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index d98fac567684..e7aba7349231 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1910,6 +1910,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &adl_uncore_init), X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_uncore_init), X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_uncore_init), + X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_uncore_init), {}, }; MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);