From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B987482 for ; Fri, 3 Jan 2025 00:32:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735864353; cv=none; b=lPkDTASZEZ7AEPkekVRFfkZZWe0nvDFayTOmQfavWPxs2dAJXhMwY3ujqK8YgshRoC47Geu/eKyK7v/dJN4kmS2HC68ief49PtuKxKlXrZLCrzwNgz9i+79vLrxntZlIYLaJApscwqb+wxIUf5SplLFEGsZKTCz+4bCuzeNjbJw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735864353; c=relaxed/simple; bh=C7Cryg3rBUC+yvizW37ExZy9SHw8V+TjV8Xx1eve9aY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pWk9oToxgNPimtzpihKoFeSdWoPwR8eE/oYQAPIXP7q54pN/lWSuukrgl3FZTZSoL284QRPgcAKJxS2GXvvPhx/pa1rCVHfsVuwR70Mv6274Th+EMcPQEt9Qvs+UFUvMBtg+IvgSzwpC211qIurN9gJjJ0QUj/MVQWeGW+OW3G8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=OeCcr7F4; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="OeCcr7F4" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2166360285dso163351655ad.1 for ; Thu, 02 Jan 2025 16:32:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1735864351; x=1736469151; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=7g+wLSi8c6UqspOT12/qWIHbcBq4WpxJE8ZGVDZG+qo=; b=OeCcr7F4HLXN9UtAfa8C5OoZewitJzC1rK7d3Tf2ug/34O4+YXfxZpQMeUChWJT8DP lCVez7MyurgDPZe4s2QtY3PgPi2Zke/iRA1KcYse+PJUGfMSvuO6lkJLIQMa3O0UvaHr uQAJd+vsmML5nwf2jzlAnzlZIi5MAXz9XYVBXltgX7C4ZOQIe7kQ/32rPndKEioTgVnN tdFQLIUFXijYA9a6pQtoRSPQy1GsBOS7COyaZwInFXFSqpxZUgdTrlh66EU9Rx91Fx+5 evYMo+sBVFQrViADB3oh/NTy2ofhnv825z4HunIn8piWFK09Ffvl16PNOc9scyaF4luu T5+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735864351; x=1736469151; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=7g+wLSi8c6UqspOT12/qWIHbcBq4WpxJE8ZGVDZG+qo=; b=A63weZeh11kbLUW83iL3p6QiJfDIvn9C+pnJiNbqbQzlk28JGHKipxckLzrtiDimZ7 wzQgXr2v5n72xMudHy5tTmBAnbmkfULsW75TALBNZ/a7qgPznIIy8uvqaOEDcQLS2JLn B+YHjnfHywhnuSNuTx6a+Js+vZ7ZN9b5kghogohxCLR1cwpxJ0JoNLeS4iS9FkcW/kn2 vD94/nq5Ux6jznfYcTszpDEXP2C4+mZhU5KtYB3r49qdOO7kft6vDYIyQuTAqL+wzcF6 O1TQdO4vXr6KyQAhSwr1C8D14IeC66pvHI8Gw1h9eZpv+KWGjnFcUZ2GTWETOvylxR92 wARg== X-Forwarded-Encrypted: i=1; AJvYcCVqcsBXmg6LHrqcJvCa2slCEUfd0mvkYpvXZ2D9f498DRAg6gQs0gXGjHgMPBJHjqxbru1R5RpfqUN2FH0=@vger.kernel.org X-Gm-Message-State: AOJu0YzeK/nL6hz7sqxAEha0xIkdl0d16tVMUY1vq+LHNGV+5Lx2K13q Y9hdIpVI8a9DiikuB58twVBun4cVhwUKLLxTk3lPv6c1s8Y1kFkiMahkbCR/Y+M= X-Gm-Gg: ASbGncuaPWV5fBUlq952+mYjm2ViS7wxrftnR4t+Ck1VJLwazNmOwczRSgDdvfCJ9Kg TN3MAZICX+PpD0SMzDj5qzbzIZyvmICXp8IkKL0d3cRtPfQBL7P1qLe9Dz3YyawUe27eLq0GrIx pVbxg5wW0IHfagPPQAHQ4wlwt23puX4ceOJ7f85BRbVOILHmHNIKjkUGdNbOQIx+3sg3RXlvL4N KxSTudSt5yee1SW8xWVXU3qUaknwlREJIs5k/hiO8IvEpKt219w X-Google-Smtp-Source: AGHT+IG3sPQtyi5nkFmQ3CmrthpTZfdWuyQXeZ4UGYJicox25LifDSU88z0mlPQiLhfTtFUIuF2xOA== X-Received: by 2002:a17:902:f54e:b0:216:6c88:efd9 with SMTP id d9443c01a7336-219e6e9a3a1mr589504795ad.15.1735864350978; Thu, 02 Jan 2025 16:32:30 -0800 (PST) Received: from ghost ([2601:647:6700:64d0:e7aa:b727:e049:3265]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9f6156sm226459435ad.209.2025.01.02.16.32.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 16:32:30 -0800 (PST) Date: Thu, 2 Jan 2025 16:32:28 -0800 From: Charlie Jenkins To: Conor Dooley Cc: linux-riscv@lists.infradead.org, Conor Dooley , xiao.w.wang@intel.com, Andrew Jones , pulehui@huawei.com, Paul Walmsley , Palmer Dabbelt , linux-kernel@vger.kernel.org, Samuel Holland , Pu Lehui , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Subject: Re: [PATCH v4 2/2] RISC-V: separate Zbb optimisations requiring and not requiring toolchain support Message-ID: References: <20241024-aspire-rectify-9982da6943e5@spud> <20241024-chump-freebase-d26b6d81af33@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241024-chump-freebase-d26b6d81af33@spud> On Thu, Oct 24, 2024 at 11:19:41AM +0100, Conor Dooley wrote: > From: Conor Dooley > > It seems a bit ridiculous to require toolchain support for BPF to > assemble Zbb instructions, so move the dependency on toolchain support > for Zbb optimisations out of the Kconfig option and to the callsites. > > Zbb support has always depended on alternatives, so while adjusting the > config options guarding optimisations, remove any checks for > whether or not alternatives are enabled. > > Reviewed-by: Andrew Jones Reviewed-by: Charlie Jenkins > Signed-off-by: Conor Dooley > --- > arch/riscv/Kconfig | 4 ++-- > arch/riscv/include/asm/arch_hweight.h | 6 +++--- > arch/riscv/include/asm/bitops.h | 4 ++-- > arch/riscv/include/asm/checksum.h | 3 +-- > arch/riscv/lib/csum.c | 21 +++------------------ > arch/riscv/lib/strcmp.S | 5 +++-- > arch/riscv/lib/strlen.S | 5 +++-- > arch/riscv/lib/strncmp.S | 5 +++-- > 8 files changed, 20 insertions(+), 33 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 278a38c94c5a6..6ec7a500a25ff 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -664,12 +664,12 @@ config RISCV_ISA_ZBA > > config RISCV_ISA_ZBB > bool "Zbb extension support for bit manipulation instructions" > - depends on TOOLCHAIN_HAS_ZBB > depends on RISCV_ALTERNATIVE > default y > help > Add support for enabling optimisations in the kernel when the > - Zbb extension is detected at boot. > + Zbb extension is detected at boot. Some optimisations may > + additionally depend on toolchain support for Zbb. > > The Zbb extension provides instructions to accelerate a number > of bit-specific operations (count bit population, sign extending, > diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h > index 613769b9cdc90..0e7cdbbec8efd 100644 > --- a/arch/riscv/include/asm/arch_hweight.h > +++ b/arch/riscv/include/asm/arch_hweight.h > @@ -19,7 +19,7 @@ > > static __always_inline unsigned int __arch_hweight32(unsigned int w) > { > -#ifdef CONFIG_RISCV_ISA_ZBB > +#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > @@ -50,7 +50,7 @@ static inline unsigned int __arch_hweight8(unsigned int w) > #if BITS_PER_LONG == 64 > static __always_inline unsigned long __arch_hweight64(__u64 w) > { > -# ifdef CONFIG_RISCV_ISA_ZBB > +#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > @@ -64,7 +64,7 @@ static __always_inline unsigned long __arch_hweight64(__u64 w) > return w; > > legacy: > -# endif > +#endif > return __sw_hweight64(w); > } > #else /* BITS_PER_LONG == 64 */ > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > index fae152ea0508d..410e2235d6589 100644 > --- a/arch/riscv/include/asm/bitops.h > +++ b/arch/riscv/include/asm/bitops.h > @@ -15,7 +15,7 @@ > #include > #include > > -#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) > +#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) > #include > #include > #include > @@ -175,7 +175,7 @@ static __always_inline int variable_fls(unsigned int x) > variable_fls(x_); \ > }) > > -#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */ > +#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */ > > #include > #include > diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h > index 88e6f1499e889..da378856f1d59 100644 > --- a/arch/riscv/include/asm/checksum.h > +++ b/arch/riscv/include/asm/checksum.h > @@ -49,8 +49,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > * ZBB only saves three instructions on 32-bit and five on 64-bit so not > * worth checking if supported without Alternatives. > */ > - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > - IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) { > unsigned long fold_temp; > > asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c > index 7fb12c59e5719..9408f50ca59a8 100644 > --- a/arch/riscv/lib/csum.c > +++ b/arch/riscv/lib/csum.c > @@ -40,12 +40,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, > uproto = (__force unsigned int)htonl(proto); > sum += uproto; > > - /* > - * Zbb support saves 4 instructions, so not worth checking without > - * alternatives if supported > - */ > - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > - IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) { > unsigned long fold_temp; > > /* > @@ -157,12 +152,7 @@ do_csum_with_alignment(const unsigned char *buff, int len) > csum = do_csum_common(ptr, end, data); > > #ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT > - /* > - * Zbb support saves 6 instructions, so not worth checking without > - * alternatives if supported > - */ > - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > - IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) { > unsigned long fold_temp; > > /* > @@ -244,12 +234,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) > end = (const unsigned long *)(buff + len); > csum = do_csum_common(ptr, end, data); > > - /* > - * Zbb support saves 6 instructions, so not worth checking without > - * alternatives if supported > - */ > - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > - IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) { > unsigned long fold_temp; > > /* > diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S > index 57a5c00662315..65027e742af15 100644 > --- a/arch/riscv/lib/strcmp.S > +++ b/arch/riscv/lib/strcmp.S > @@ -8,7 +8,8 @@ > /* int strcmp(const char *cs, const char *ct) */ > SYM_FUNC_START(strcmp) > > - ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB) > + __ALTERNATIVE_CFG("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, > + IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) > > /* > * Returns > @@ -43,7 +44,7 @@ SYM_FUNC_START(strcmp) > * The code was published as part of the bitmanip manual > * in Appendix A. > */ > -#ifdef CONFIG_RISCV_ISA_ZBB > +#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > strcmp_zbb: > > .option push > diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S > index 962983b73251e..eb4d2b7ed22b6 100644 > --- a/arch/riscv/lib/strlen.S > +++ b/arch/riscv/lib/strlen.S > @@ -8,7 +8,8 @@ > /* int strlen(const char *s) */ > SYM_FUNC_START(strlen) > > - ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB) > + __ALTERNATIVE_CFG("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, > + IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) > > /* > * Returns > @@ -33,7 +34,7 @@ SYM_FUNC_START(strlen) > /* > * Variant of strlen using the ZBB extension if available > */ > -#ifdef CONFIG_RISCV_ISA_ZBB > +#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > strlen_zbb: > > #ifdef CONFIG_CPU_BIG_ENDIAN > diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S > index 7b2d0ff9ed6c7..062000c468c83 100644 > --- a/arch/riscv/lib/strncmp.S > +++ b/arch/riscv/lib/strncmp.S > @@ -8,7 +8,8 @@ > /* int strncmp(const char *cs, const char *ct, size_t count) */ > SYM_FUNC_START(strncmp) > > - ALTERNATIVE("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB) > + __ALTERNATIVE_CFG("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB, > + IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) > > /* > * Returns > @@ -46,7 +47,7 @@ SYM_FUNC_START(strncmp) > /* > * Variant of strncmp using the ZBB extension if available > */ > -#ifdef CONFIG_RISCV_ISA_ZBB > +#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) > strncmp_zbb: > > .option push > -- > 2.45.2 >