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AJvYcCVexp8g+xNdRj/o3Nuo1rYadG6/WT7qmlZhH4EGrUcNVZkguub+DriArjjnzOY2Jn+o4kUAmthnD6d5LEc=@vger.kernel.org X-Gm-Message-State: AOJu0YzVL/I2p7cOexthZSTxFaV75SKwpV1h11JBPZ7cfhcDEUYVMeq7 Up4IFXE79jWp3bvuBqBuZ/x3hEXT1rfaf0ZzY//FqScP5zHJ882/YVEzTBn6eCVVVYiTdL2J+e8 3ow== X-Google-Smtp-Source: AGHT+IG36Tj1MEd1do7PTJpeYtiE0FYql983/qkYoONMBWTQeV01lDzjCo5AiSoGdXiaTtk8/FahyMrvRfg= X-Received: from pjbsd5.prod.google.com ([2002:a17:90b:5145:b0:2ef:8055:93d9]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3cc6:b0:2ee:aa95:6de9 with SMTP id 98e67ed59e1d1-2f452eed7e1mr90148916a91.33.1736188167401; Mon, 06 Jan 2025 10:29:27 -0800 (PST) Date: Mon, 6 Jan 2025 10:29:25 -0800 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> <287e8a60e302929588eaf095584838fa745d69ac.camel@surriel.com> Message-ID: Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions From: Sean Christopherson To: Jann Horn Cc: Rik van Riel , Paolo Bonzini , KVM list , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Mon, Jan 06, 2025, Jann Horn wrote: > +KVM/SVM folks in case they know more about how enabling CPU features > interacts with virtualization; original patch is at > https://lore.kernel.org/all/20241230175550.4046587-12-riel@surriel.com/ >=20 > On Sat, Jan 4, 2025 at 4:08=E2=80=AFAM Rik van Riel wr= ote: > > On Fri, 2025-01-03 at 18:49 +0100, Jann Horn wrote: > > > On Mon, Dec 30, 2024 at 6:53=E2=80=AFPM Rik van Riel > > > > only those upper-level entries that lead to the target PTE in > > > > the page table hierarchy, leaving unrelated upper-level entries > > > > intact. > > > > > > How does this patch interact with KVM SVM guests? > > > In particular, will this patch cause TLB flushes performed by guest > > > kernels to behave differently? No. EFER is context switched by hardware on VMRUN and #VMEXIT, i.e. the gu= est runs with its own EFER, and thus will get the targeted flushes if and only = if the hypervisor virtualizes EFER.TCE *and* the guest explicitly enables EFER= .TCE. > > That is a good question. > > > > A Linux guest should be fine, since Linux already flushes the parts of = the > > TLB where page tables are being freed. > > > > I don't know whether this could potentially break some non-Linux guests= , > > though.