Re: [PATCH 7/7] arm64: dts: qcom: x1e80100: enable rtc

Jens Glathe
2025-01-20T18:12:15Z

Hi Johan,

On 20.01.25 15:41, Johan Hovold wrote:
> On many Qualcomm platforms the PMIC RTC control and time registers are
> read-only so that the RTC time can not be updated. Instead an offset
> needs be stored in some machine-specific non-volatile memory, which a
> driver can take into account.
>
> On X1E based Windows on Arm machines the offset is stored in a Qualcomm
> specific UEFI variable.
>
> Unlike on previous platforms the alarm registers are also unaccessible
> on X1E as they are owned by the ADSP.
>
> Assume all X1E machines use similar firmware and enable the RTC in the
> PMIC dtsi for now.
>
> Based on a patch by Jonathan Marek. [1]
>
> Link: https://lore.kernel.org/r/20241015004945.3676-4-jonathan@marek.ca # [1]
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
> index 5b54ee79f048..051fb3a304b9 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
> @@ -223,8 +223,8 @@ pmk8550_rtc: rtc@6100 {
> reg = <0x6100>, <0x6200>;
> reg-names = "rtc", "alarm";
> interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
> - /* Not yet sure what blocks access */
> - status = "reserved";
> + qcom,no-alarm; /* alarm owned by ADSP */
> + qcom,uefi-rtc-info;
> };
>
> pmk8550_sdam_2: nvram@7100 {

works nicely on SnapDragon Dev Kit X1E001DE. Thank you!

Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>

with best regards

Jens Glathe