From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F2392E406 for ; Tue, 21 Jan 2025 07:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737444873; cv=none; b=trC0Py1+8akAH9Q5hCOPzXRY+9OKvWPsjgqG4gBzOfmHYU9qJcFqWI5ED5HHNFb9HsF/qsYTXO0wqHcTDLi1hwblwdm5m/2gZfO+TaGvoPidtsDtZ4Hl+dKFpa0oyPe9+SwK2xCWpRZvjqmDtlIYmp5h4ldgrQ57/OnvCGDH6DM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737444873; c=relaxed/simple; bh=XxIEP8Zh94wTmswCaGaNtN+IlKYVa8BvhTg9xl6mrWQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RmxDwiBfAWB3VK3v4ARI2vA+9NZlk1luz8f3DSqf/yDMhiN2cnzuTB9YUAC+R6fOTmSwZIxvtE5iDJoVVJjfT7q5ldbC1EzqZKZOTZ+2dRa/PFK2V9SZ7regDVKcxA5dwui6ONjdZSP+jR1BPYnp9ZCbtQsisuuMPLOYIts7M+E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gsxZjfCK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gsxZjfCK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD30AC4CEDF; Tue, 21 Jan 2025 07:34:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737444872; bh=XxIEP8Zh94wTmswCaGaNtN+IlKYVa8BvhTg9xl6mrWQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=gsxZjfCKenqLr0ZyYtX9CpWvWpsw5J1/9EmuxU2bKFvUzCD6LwxKddAAP+BLmNgIp PAbW+kc9MPEo3QVHPmUWI4zD8+ZhIHdxO+0fZ6D9ITmD5nYAM09cYfm+vG5CoJtw4H 2x+WjZtd9umrpEnU6wBX3NWPEM0vSWaYnXAr85i6iXBALSCItLQLTL7kcAt0MsyB21 V1HT2jEJPJ7lVrj4zYLe+f/JPqemUenVbK+3o0T6eEvsV1ekJBTVLvIo6cRWH64JRF KNXCdZU1+ixGeRraQM+R1qg44pd7mrN+EdFuW0qQuv4SGeJX3z0oDCQ0vL3OJ8C8wp JLHV7aqpo/D5Q== Date: Tue, 21 Jan 2025 08:34:29 +0100 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, the arch/x86 maintainers Subject: Re: [GIT PULL] x86/cleanups for v6.14 Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: * Ingo Molnar wrote: > Linus, > > Please pull the latest x86/cleanups Git tree from: > > git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-cleanups-2025-01-21 > > # HEAD: 0094014be0cd75273ef7f2934c17fb8cffd4db6e x86/ioapic: Remove a stray tab in the IO-APIC type string > > Miscellaneous x86 cleanups and typo fixes, and also the removal > of the "disablelapic" boot parameter. Merge note: if you've pulled x86/sev from Boris already, then there will be a new conflict in arch/x86/include/asm/cpufeatures.h due to overlapping (but compatible) changes to the same lines of code. My conflict resolution is below, for reference. Thanks, Ingo =======================> Merge branch 'x86/cleanups' into tmp.tmp Conflicts: arch/x86/include/asm/cpufeatures.h Signed-off-by: Ingo Molnar diff --cc arch/x86/include/asm/cpufeatures.h index 8b55685255d6,09e1e54676f4..9746e75a1866 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@@ -443,18 -443,15 +443,18 @@@ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* Speculative Store Bypass Disable */ /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */ - #define X86_FEATURE_SME (19*32+ 0) /* "sme" AMD Secure Memory Encryption */ - #define X86_FEATURE_SEV (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */ + #define X86_FEATURE_SME (19*32+ 0) /* "sme" Secure Memory Encryption */ + #define X86_FEATURE_SEV (19*32+ 1) /* "sev" Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */ - #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */ - #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */ + #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */ + #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ - #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */ - #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */ + #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */ + #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */ +#define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ +#define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ +#define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages */ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */