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Tue, 21 Jan 2025 01:55:14 -0800 (PST) Date: Tue, 21 Jan 2025 11:55:13 +0200 From: Abel Vesa To: Wenbin Yao Cc: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] phy: qcom: pcie: Determine has_nocsr_reset dynamically Message-ID: References: <20250121094140.4006801-1-quic_wenbyao@quicinc.com> <20250121094140.4006801-2-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250121094140.4006801-2-quic_wenbyao@quicinc.com> On 25-01-21 17:41:39, Wenbin Yao wrote: > From: Konrad Dybcio > > Decide the in-driver logic based on whether the nocsr reset is present > and defer checking the appropriateness of that to dt-bindings to save > on boilerplate. > > Reset controller APIs are fine consuming a nullptr, so no additional > checks are necessary there. > > Signed-off-by: Konrad Dybcio > Signed-off-by: Wenbin Yao Reviewed-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +++++++----------- > 1 file changed, 7 insertions(+), 11 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index 873f2f9844c6..ac42e4b01065 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -2793,8 +2793,6 @@ struct qmp_phy_cfg { > > bool skip_start_delay; > > - bool has_nocsr_reset; > - > /* QMP PHY pipe clock interface rate */ > unsigned long pipe_clock_rate; > > @@ -3685,7 +3683,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { > > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .phy_status = PHYSTATUS_4_20, > - .has_nocsr_reset = true, > > /* 20MHz PHY AUX Clock */ > .aux_clock_rate = 20000000, > @@ -3718,7 +3715,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { > > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .phy_status = PHYSTATUS_4_20, > - .has_nocsr_reset = true, > > /* 20MHz PHY AUX Clock */ > .aux_clock_rate = 20000000, > @@ -3836,7 +3832,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { > > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .phy_status = PHYSTATUS_4_20, > - .has_nocsr_reset = true, > }; > > static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { > @@ -3870,7 +3865,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { > > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .phy_status = PHYSTATUS_4_20, > - .has_nocsr_reset = true, > }; > > static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { > @@ -3902,7 +3896,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { > > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .phy_status = PHYSTATUS_4_20, > - .has_nocsr_reset = true, > }; > > static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) > @@ -4203,11 +4196,14 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) > if (ret) > return dev_err_probe(dev, ret, "failed to get resets\n"); > > - if (cfg->has_nocsr_reset) { > - qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); > - if (IS_ERR(qmp->nocsr_reset)) > + qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); > + if (IS_ERR(qmp->nocsr_reset)) { > + if (PTR_ERR(qmp->nocsr_reset) == -ENOENT || > + PTR_ERR(qmp->nocsr_reset) == -EINVAL) > + qmp->nocsr_reset = NULL; > + else > return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), > - "failed to get no-csr reset\n"); > + "failed to get no-csr reset\n"); > } > > return 0; > -- > 2.34.1 >