[PATCH 0/3] drm/i915/gvt: Deadcoding

[PATCH 0/3] drm/i915/gvt: Deadcoding

[linux]

From: "Dr. David Alan Gilbert" <linux@treblig.org>

Remove a bunch of long unused functions from
the gvt code.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>


Dr. David Alan Gilbert (3):
  drm/i915/gvt: Remove intel_gvt_ggtt_h2g<->index
  drm/i915/gvt: Remove unused intel_vgpu_decode_sprite_plane
  drm/i915/gvt: Remove unused intel_gvt_in_force_nonpriv_whitelist

 drivers/gpu/drm/i915/gvt/fb_decoder.c | 117 --------------------------
 drivers/gpu/drm/i915/gvt/fb_decoder.h |   2 -
 drivers/gpu/drm/i915/gvt/gtt.c        |  66 ---------------
 drivers/gpu/drm/i915/gvt/gvt.h        |   6 --
 drivers/gpu/drm/i915/gvt/handlers.c   |  17 ----
 drivers/gpu/drm/i915/gvt/mmio.h       |   3 -
 6 files changed, 211 deletions(-)

-- 
2.47.1

[PATCH 1/3] drm/i915/gvt: Remove intel_gvt_ggtt_h2g<->index

[linux]

From: "Dr. David Alan Gilbert" <linux@treblig.org>

intel_gvt_ggtt_h2g_index() and intel_gvt_ggtt_index_g2h() were
added in 2016 by
commit 2707e4446688 ("drm/i915/gvt: vGPU graphics memory virtualization")
but haven't been used.

Remove them.

They were the only users of intel_gvt_ggtt_gmadr_g2h() and
intel_gvt_ggtt_gmadr_h2g().

Remove them.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 66 ----------------------------------
 drivers/gpu/drm/i915/gvt/gvt.h |  6 ----
 2 files changed, 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 1bce1493b86f..464fb17e82ee 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -71,72 +71,6 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
 	return false;
 }
 
-/* translate a guest gmadr to host gmadr */
-int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
-{
-	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
-
-	if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
-		     "invalid guest gmadr %llx\n", g_addr))
-		return -EACCES;
-
-	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
-		*h_addr = vgpu_aperture_gmadr_base(vgpu)
-			  + (g_addr - vgpu_aperture_offset(vgpu));
-	else
-		*h_addr = vgpu_hidden_gmadr_base(vgpu)
-			  + (g_addr - vgpu_hidden_offset(vgpu));
-	return 0;
-}
-
-/* translate a host gmadr to guest gmadr */
-int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
-{
-	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
-
-	if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
-		     "invalid host gmadr %llx\n", h_addr))
-		return -EACCES;
-
-	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
-		*g_addr = vgpu_aperture_gmadr_base(vgpu)
-			+ (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
-	else
-		*g_addr = vgpu_hidden_gmadr_base(vgpu)
-			+ (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
-	return 0;
-}
-
-int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
-			     unsigned long *h_index)
-{
-	u64 h_addr;
-	int ret;
-
-	ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
-				       &h_addr);
-	if (ret)
-		return ret;
-
-	*h_index = h_addr >> I915_GTT_PAGE_SHIFT;
-	return 0;
-}
-
-int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
-			     unsigned long *g_index)
-{
-	u64 g_addr;
-	int ret;
-
-	ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
-				       &g_addr);
-	if (ret)
-		return ret;
-
-	*g_index = g_addr >> I915_GTT_PAGE_SHIFT;
-	return 0;
-}
-
 #define gtt_type_is_entry(type) \
 	(type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
 	 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 2c95aeef4e41..8580c6d057e7 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -531,12 +531,6 @@ int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num);
 	    gvt_gmadr_is_hidden(gvt, gmadr))
 
 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
-int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
-int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
-int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
-			     unsigned long *h_index);
-int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
-			     unsigned long *g_index);
 
 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
 		bool primary);
-- 
2.47.1

[PATCH 2/3] drm/i915/gvt: Remove unused intel_vgpu_decode_sprite_plane

[linux]

From: "Dr. David Alan Gilbert" <linux@treblig.org>

intel_vgpu_decode_sprite_plane() was added in 2017 by
commit 9f31d1063b43 ("drm/i915/gvt: Add framebuffer decoder support")
but has remained unused.

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
---
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 117 --------------------------
 drivers/gpu/drm/i915/gvt/fb_decoder.h |   2 -
 2 files changed, 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index c454e25b2b0f..a37322914f5e 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -395,120 +395,3 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
 	return 0;
 }
-
-#define SPRITE_FORMAT_NUM	(1 << 3)
-
-static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
-	[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
-	[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
-	[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
-	[0x4] = {DRM_FORMAT_AYUV, 32,
-		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
-};
-
-/**
- * intel_vgpu_decode_sprite_plane - Decode sprite plane
- * @vgpu: input vgpu
- * @plane: sprite plane to save decoded info
- * This function is called for decoding plane
- *
- * Returns:
- * 0 on success, non-zero if failed.
- */
-int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
-	struct intel_vgpu_sprite_plane_format *plane)
-{
-	u32 val, fmt;
-	u32 color_order, yuv_order;
-	int drm_format;
-	int pipe;
-
-	pipe = get_active_pipe(vgpu);
-	if (pipe >= I915_MAX_PIPES)
-		return -ENODEV;
-
-	val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
-	plane->enabled = !!(val & SPRITE_ENABLE);
-	if (!plane->enabled)
-		return -ENODEV;
-
-	plane->tiled = !!(val & SPRITE_TILED);
-	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
-	yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
-				_SPRITE_YUV_ORDER_SHIFT;
-
-	fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
-	if (!sprite_pixel_formats[fmt].bpp) {
-		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
-		return -EINVAL;
-	}
-	plane->hw_format = fmt;
-	plane->bpp = sprite_pixel_formats[fmt].bpp;
-	drm_format = sprite_pixel_formats[fmt].drm_format;
-
-	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
-	 * BGR depending on the state of the color_order field
-	 */
-	if (!color_order) {
-		if (drm_format == DRM_FORMAT_XRGB2101010)
-			drm_format = DRM_FORMAT_XBGR2101010;
-		else if (drm_format == DRM_FORMAT_XRGB8888)
-			drm_format = DRM_FORMAT_XBGR8888;
-	}
-
-	if (drm_format == DRM_FORMAT_YUV422) {
-		switch (yuv_order) {
-		case 0:
-			drm_format = DRM_FORMAT_YUYV;
-			break;
-		case 1:
-			drm_format = DRM_FORMAT_UYVY;
-			break;
-		case 2:
-			drm_format = DRM_FORMAT_YVYU;
-			break;
-		case 3:
-			drm_format = DRM_FORMAT_VYUY;
-			break;
-		default:
-			/* yuv_order has only 2 bits */
-			break;
-		}
-	}
-
-	plane->drm_format = drm_format;
-
-	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
-	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
-		return  -EINVAL;
-
-	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
-	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
-		gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
-				plane->base);
-		return  -EINVAL;
-	}
-
-	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
-				_SPRITE_STRIDE_MASK;
-
-	val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
-	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
-		_SPRITE_SIZE_HEIGHT_SHIFT;
-	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
-		_SPRITE_SIZE_WIDTH_SHIFT;
-	plane->height += 1;	/* raw height is one minus the real value */
-	plane->width += 1;	/* raw width is one minus the real value */
-
-	val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
-	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
-	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
-
-	val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
-	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
-			   _SPRITE_OFFSET_START_X_SHIFT;
-	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
-			   _SPRITE_OFFSET_START_Y_SHIFT;
-
-	return 0;
-}
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h
index fa6503900c84..436d43c0087b 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.h
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
@@ -156,7 +156,5 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 	struct intel_vgpu_primary_plane_format *plane);
 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 	struct intel_vgpu_cursor_plane_format *plane);
-int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
-	struct intel_vgpu_sprite_plane_format *plane);
 
 #endif
-- 
2.47.1

[PATCH 3/3] drm/i915/gvt: Remove unused intel_gvt_in_force_nonpriv_whitelist

[linux]

From: "Dr. David Alan Gilbert" <linux@treblig.org>

The last use of intel_gvt_in_force_nonpriv_whitelist() was
removed in 2020 by
commit 02dd2b12a685 ("drm/i915/gvt: unify lri cmd handler and mmio
handlers")

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 17 -----------------
 drivers/gpu/drm/i915/gvt/mmio.h     |  3 ---
 2 files changed, 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9494d812c00a..7aca66dd12cd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3113,23 +3113,6 @@ int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	return 0;
 }
 
-/**
- * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
- * force-nopriv register
- *
- * @gvt: a GVT device
- * @offset: register offset
- *
- * Returns:
- * True if the register is in force-nonpriv whitelist;
- * False if outside;
- */
-bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
-					  unsigned int offset)
-{
-	return in_whitelist(offset);
-}
-
 /**
  * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
  * @vgpu: a vGPU
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 32ebacb078e8..3dc912aba80b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -96,9 +96,6 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 				  void *p_data, unsigned int bytes);
 
-bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
-					  unsigned int offset);
-
 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
 			   void *pdata, unsigned int bytes, bool is_read);
 
-- 
2.47.1

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Dr. David Alan Gilbert]

Note: zhenyuw@linux.intel.com's address bounces:

> The following message to <zhenyuw@linux.intel.com> was undeliverable.
> The reason for the problem:
> 5.1.0 - Unknown address error 550-'5.1.1 <zhenyuw@linux.intel.com>: Recipient address rejected: User unknown in
+virtual mailbox table'

* linux@treblig.org (linux@treblig.org) wrote:
> From: "Dr. David Alan Gilbert" <linux@treblig.org>
> 
> Remove a bunch of long unused functions from
> the gvt code.
> 
> Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
> 
> 
> Dr. David Alan Gilbert (3):
>   drm/i915/gvt: Remove intel_gvt_ggtt_h2g<->index
>   drm/i915/gvt: Remove unused intel_vgpu_decode_sprite_plane
>   drm/i915/gvt: Remove unused intel_gvt_in_force_nonpriv_whitelist
> 
>  drivers/gpu/drm/i915/gvt/fb_decoder.c | 117 --------------------------
>  drivers/gpu/drm/i915/gvt/fb_decoder.h |   2 -
>  drivers/gpu/drm/i915/gvt/gtt.c        |  66 ---------------
>  drivers/gpu/drm/i915/gvt/gvt.h        |   6 --
>  drivers/gpu/drm/i915/gvt/handlers.c   |  17 ----
>  drivers/gpu/drm/i915/gvt/mmio.h       |   3 -
>  6 files changed, 211 deletions(-)
> 
> -- 
> 2.47.1
> 
-- 
 -----Open up your eyes, open up your mind, open up your code -------   
/ Dr. David Alan Gilbert    |       Running GNU/Linux       | Happy  \ 
\        dave @ treblig.org |                               | In Hex /
 \ _________________________|_____ http://www.treblig.org   |_______/

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Zhenyu Wang]

On Sun, Dec 22, 2024 at 12:20:40AM +0000, linux@treblig.org wrote:
> From: "Dr. David Alan Gilbert" <linux@treblig.org>
> 
> Remove a bunch of long unused functions from
> the gvt code.
> 
> Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
> 
> 
> Dr. David Alan Gilbert (3):
>   drm/i915/gvt: Remove intel_gvt_ggtt_h2g<->index
>   drm/i915/gvt: Remove unused intel_vgpu_decode_sprite_plane
>   drm/i915/gvt: Remove unused intel_gvt_in_force_nonpriv_whitelist
>

All three cleanups are fine with me.

Reviewed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>

>  drivers/gpu/drm/i915/gvt/fb_decoder.c | 117 --------------------------
>  drivers/gpu/drm/i915/gvt/fb_decoder.h |   2 -
>  drivers/gpu/drm/i915/gvt/gtt.c        |  66 ---------------
>  drivers/gpu/drm/i915/gvt/gvt.h        |   6 --
>  drivers/gpu/drm/i915/gvt/handlers.c   |  17 ----
>  drivers/gpu/drm/i915/gvt/mmio.h       |   3 -
>  6 files changed, 211 deletions(-)
> 
> -- 
> 2.47.1
> 

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Zhenyu Wang]

On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
> Note: zhenyuw@linux.intel.com's address bounces:
> 

yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
queue up my address change patch yet. Rodrigo?

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Rodrigo Vivi]

On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
> > Note: zhenyuw@linux.intel.com's address bounces:
> > 
> 
> yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
> queue up my address change patch yet. Rodrigo?

pushed to drm-intel-next now, although I was assuming this to come
on a gvt pull request...

what about this patch here? coming in a PR or should I take this
directly at drm-intel-next as well?

Thanks,
Rodrigo.

GVT-g status (was: Re: [PATCH 0/3] drm/i915/gvt: Deadcoding)

[Jani Nikula]

On Thu, 09 Jan 2025, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
>> On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
>> > Note: zhenyuw@linux.intel.com's address bounces:
>> > 
>> 
>> yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
>> queue up my address change patch yet. Rodrigo?
>
> pushed to drm-intel-next now, although I was assuming this to come
> on a gvt pull request...
>
> what about this patch here? coming in a PR or should I take this
> directly at drm-intel-next as well?

AFAICT the last gvt-next pull request was more than two years ago and
gvt-fixes slightly less than one year ago.

There's a single cleanup commit in gvt-next applied two years ago for
which there hasn't been a pull request.

The GVT github page [1] says, "This repository has been archived by the
owner on Oct 3, 2024. It is now read-only." The intel-gvt-dev mailing
list [2] appears to be mostly spam.

Seems to me something like this would be appropriate:

diff --git a/MAINTAINERS b/MAINTAINERS
index 1c3eab5d2b1a..161206fdaf05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11557,11 +11557,10 @@ F:	drivers/gpio/gpio-tangier.h
 INTEL GVT-g DRIVERS (Intel GPU Virtualization)
 M:	Zhenyu Wang <zhenyuw.linux@gmail.com>
 M:	Zhi Wang <zhi.wang.linux@gmail.com>
-L:	intel-gvt-dev@lists.freedesktop.org
 L:	intel-gfx@lists.freedesktop.org
-S:	Supported
+S:	Maintained
 W:	https://github.com/intel/gvt-linux/wiki
-T:	git https://github.com/intel/gvt-linux.git
+T:	git https://gitlab.freedesktop.org/drm/i915/kernel.git
 F:	drivers/gpu/drm/i915/gvt/
 
 INTEL HID EVENT DRIVER

But I don't think it would be far from the truth to have "S: Odd Fixes"
either. And the extreme would be to just remove the whole maintainers
entry and have it fall back to the i915 entry.

Thoughts?


BR,
Jani.


[1] https://github.com/intel/gvt-linux/
[2] https://lists.freedesktop.org/archives/intel-gvt-dev/


-- 
Jani Nikula, Intel

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Zhenyu Wang]

On Thu, Jan 09, 2025 at 04:10:24PM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> > On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
> > > Note: zhenyuw@linux.intel.com's address bounces:
> > > 
> > 
> > yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
> > queue up my address change patch yet. Rodrigo?
> 
> pushed to drm-intel-next now, although I was assuming this to come
> on a gvt pull request...
> 
> what about this patch here? coming in a PR or should I take this
> directly at drm-intel-next as well?
> 

Please just include this directly. I don't really have plan to send extra PR
for gvt changes but only help to review.

Thanks!

Re: GVT-g status (was: Re: [PATCH 0/3] drm/i915/gvt: Deadcoding)

[Zhenyu Wang]

On Fri, Jan 10, 2025 at 12:49:27PM +0200, Jani Nikula wrote:
> On Thu, 09 Jan 2025, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> >> On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
> >> > Note: zhenyuw@linux.intel.com's address bounces:
> >> > 
> >> 
> >> yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
> >> queue up my address change patch yet. Rodrigo?
> >
> > pushed to drm-intel-next now, although I was assuming this to come
> > on a gvt pull request...
> >
> > what about this patch here? coming in a PR or should I take this
> > directly at drm-intel-next as well?
> 
> AFAICT the last gvt-next pull request was more than two years ago and
> gvt-fixes slightly less than one year ago.
> 
> There's a single cleanup commit in gvt-next applied two years ago for
> which there hasn't been a pull request.
> 
> The GVT github page [1] says, "This repository has been archived by the
> owner on Oct 3, 2024. It is now read-only." The intel-gvt-dev mailing
> list [2] appears to be mostly spam.
> 
> Seems to me something like this would be appropriate:
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1c3eab5d2b1a..161206fdaf05 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11557,11 +11557,10 @@ F:	drivers/gpio/gpio-tangier.h
>  INTEL GVT-g DRIVERS (Intel GPU Virtualization)
>  M:	Zhenyu Wang <zhenyuw.linux@gmail.com>
>  M:	Zhi Wang <zhi.wang.linux@gmail.com>
> -L:	intel-gvt-dev@lists.freedesktop.org
>  L:	intel-gfx@lists.freedesktop.org
> -S:	Supported
> +S:	Maintained
>  W:	https://github.com/intel/gvt-linux/wiki
> -T:	git https://github.com/intel/gvt-linux.git
> +T:	git https://gitlab.freedesktop.org/drm/i915/kernel.git
>  F:	drivers/gpu/drm/i915/gvt/
>

Looks fine with me.

Acked-by: Zhenyu Wang <zhenyuw.linux@gmail.com>

>  INTEL HID EVENT DRIVER
> 
> But I don't think it would be far from the truth to have "S: Odd Fixes"
> either. And the extreme would be to just remove the whole maintainers
> entry and have it fall back to the i915 entry.
> 
> Thoughts?
>

When I left Intel, I have raised similar question to manager or related
people to see their ideas on how to keep GVT-g maintenance work for upstream,
but I didn't get real answers before my last day at Intel...So still cc some
intel gvt related people to double confirm.

For me, it's fine to remove the maintainer entry maybe only keep as reviewer?

Thanks to raise up this issue, Jani! 

Re: GVT-g status (was: Re: [PATCH 0/3] drm/i915/gvt: Deadcoding)

[Zhi Wang]

On Sat, 11 Jan 2025 14:26:01 +0900
Zhenyu Wang <zhenyuw.linux@gmail.com> wrote:

> On Fri, Jan 10, 2025 at 12:49:27PM +0200, Jani Nikula wrote:
> > On Thu, 09 Jan 2025, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > > On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> > >> On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert
> > >> wrote:
> > >> > Note: zhenyuw@linux.intel.com's address bounces:
> > >> > 
> > >> 
> > >> yeah, I've left Intel so can't use that box any more, looks
> > >> Rodrigo hasn't queue up my address change patch yet. Rodrigo?
> > >
> > > pushed to drm-intel-next now, although I was assuming this to come
> > > on a gvt pull request...
> > >
> > > what about this patch here? coming in a PR or should I take this
> > > directly at drm-intel-next as well?
> > 
> > AFAICT the last gvt-next pull request was more than two years ago
> > and gvt-fixes slightly less than one year ago.
> > 
> > There's a single cleanup commit in gvt-next applied two years ago
> > for which there hasn't been a pull request.
> > 
> > The GVT github page [1] says, "This repository has been archived by
> > the owner on Oct 3, 2024. It is now read-only." The intel-gvt-dev
> > mailing list [2] appears to be mostly spam.
> > 
> > Seems to me something like this would be appropriate:
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 1c3eab5d2b1a..161206fdaf05 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11557,11 +11557,10 @@ F:	drivers/gpio/gpio-tangier.h
> >  INTEL GVT-g DRIVERS (Intel GPU Virtualization)
> >  M:	Zhenyu Wang <zhenyuw.linux@gmail.com>
> >  M:	Zhi Wang <zhi.wang.linux@gmail.com>
> > -L:	intel-gvt-dev@lists.freedesktop.org
> >  L:	intel-gfx@lists.freedesktop.org
> > -S:	Supported
> > +S:	Maintained
> >  W:	https://github.com/intel/gvt-linux/wiki
> > -T:	git https://github.com/intel/gvt-linux.git
> > +T:	git https://gitlab.freedesktop.org/drm/i915/kernel.git
> >  F:	drivers/gpu/drm/i915/gvt/
> >
> 
> Looks fine with me.
> 
> Acked-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> 
> >  INTEL HID EVENT DRIVER
> > 
> > But I don't think it would be far from the truth to have "S: Odd
> > Fixes" either. And the extreme would be to just remove the whole
> > maintainers entry and have it fall back to the i915 entry.
> > 
> > Thoughts?
> >
> 
> When I left Intel, I have raised similar question to manager or
> related people to see their ideas on how to keep GVT-g maintenance
> work for upstream, but I didn't get real answers before my last day
> at Intel...So still cc some intel gvt related people to double
> confirm.
> 
> For me, it's fine to remove the maintainer entry maybe only keep as
> reviewer?
> 
> Thanks to raise up this issue, Jani! 
> 

Works for me as well. I am mostly doing this as a hobby on my Skylake
desktop in my spare time.

Z.

Re: [PATCH 0/3] drm/i915/gvt: Deadcoding

[Rodrigo Vivi]

On Sat, Jan 11, 2025 at 02:12:17PM +0900, Zhenyu Wang wrote:
> On Thu, Jan 09, 2025 at 04:10:24PM -0500, Rodrigo Vivi wrote:
> > On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> > > On Sun, Dec 22, 2024 at 12:25:09AM +0000, Dr. David Alan Gilbert wrote:
> > > > Note: zhenyuw@linux.intel.com's address bounces:
> > > > 
> > > 
> > > yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
> > > queue up my address change patch yet. Rodrigo?
> > 
> > pushed to drm-intel-next now, although I was assuming this to come
> > on a gvt pull request...
> > 
> > what about this patch here? coming in a PR or should I take this
> > directly at drm-intel-next as well?
> > 
> 
> Please just include this directly. I don't really have plan to send extra PR
> for gvt changes but only help to review.

pushed to drm-intel-next. Thanks

> 
> Thanks!