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From: Lukas Wunner <lukas@wunner.de>
To: "Bowman, Terry" <terry.bowman@amd.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
	linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
	dave@stgolabs.net, jonathan.cameron@huawei.com,
	dave.jiang@intel.com, alison.schofield@intel.com,
	vishal.l.verma@intel.com, dan.j.williams@intel.com,
	bhelgaas@google.com, mahesh@linux.ibm.com, oohall@gmail.com,
	Benjamin.Cheatham@amd.com, rrichter@amd.com,
	nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
	ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com,
	alucerop@amd.com
Subject: Re: [PATCH v5 03/16] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port()
Date: Wed, 15 Jan 2025 11:03:10 +0100	[thread overview]
Message-ID: <Z4eH3izmcBWYwynt@wunner.de> (raw)
In-Reply-To: <a2fc0134-5b6d-4778-aef2-4447c50eb430@amd.com>

On Tue, Jan 14, 2025 at 09:19:12AM -0600, Bowman, Terry wrote:
> On 1/13/2025 5:49 PM, Ira Weiny wrote:
> > Terry Bowman wrote:
> > > --- a/drivers/pci/pci.c
> > > +++ b/drivers/pci/pci.c
> > > @@ -5036,10 +5036,23 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
> > >  
> > >  static u16 cxl_port_dvsec(struct pci_dev *dev)
> > >  {
> > > +	if (!pcie_is_cxl(dev))
> > > +		return 0;
> > > +
> > >  	return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
> > >  					 PCI_DVSEC_CXL_PORT);
> > >  }
> > >  
> > > +bool pcie_is_cxl_port(struct pci_dev *dev)
> > > +{
> > > +	if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
> > > +	    (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
> > > +	    (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))
> > > +		return false;
> > > +
> > > +	return cxl_port_dvsec(dev);
> > 
> > Returning bool from a function which returns u16 is odd and I don't think
> > it should be coded this way.  I don't think it is wrong right now but this
> > really ought to code the pcie_is_cxl() here and leave cxl_port_dvsec()
> > alone.  Calling cxl_port_dvsec(), checking for if the dvsec exists, and
> > returning bool.
> 
> Thanks for reviewing. Is this what you are looking for here:
> 
> +bool pcie_is_cxl_port(struct pci_dev *dev)
> +{
> +	return (cxl_port_dvsec(dev) > 0);

Since cxl_port_dvsec() cannot return a negative integer,
you might as well use:

	return !!cxl_port_dvsec(dev);

However last I checked gcc generates code which implicitly turns
a number bigger than 1 into a 1 if the return type is bool.
(I had to fix a bug caused by this behavior once, see 009f8c90f571).

Thanks,

Lukas

  parent reply	other threads:[~2025-01-15 10:12 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-07 14:38 [PATCH v5 0/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-01-07 14:38 ` [PATCH v5 01/16] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-01-13 23:45   ` Ira Weiny
2025-02-06 17:01   ` Gregory Price
2025-02-07 18:35     ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 02/16] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-01-13 23:45   ` Ira Weiny
2025-02-06 17:02   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 03/16] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-01-13 23:49   ` Ira Weiny
2025-01-14 15:19     ` Bowman, Terry
2025-01-14 23:33       ` Ira Weiny
2025-01-14 23:39         ` Bowman, Terry
2025-01-16 15:35           ` Ira Weiny
2025-01-15 10:03       ` Lukas Wunner [this message]
2025-01-07 14:38 ` [PATCH v5 04/16] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-01-13 23:51   ` Ira Weiny
2025-02-06 18:18   ` Gregory Price
2025-02-07 18:50     ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 05/16] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-01-14  6:54   ` Li Ming
2025-01-14 11:20     ` Jonathan Cameron
2025-01-14 20:10       ` Bowman, Terry
2025-01-14 19:29     ` Bowman, Terry
2025-01-15  1:18       ` Li Ming
2025-01-15 14:39         ` Bowman, Terry
2025-01-16  3:15           ` Li Ming
2025-02-05  3:46             ` Bowman, Terry
2025-02-05 13:58               ` Li Ming
2025-02-05 14:22                 ` Bowman, Terry
2025-01-14 16:35   ` Ira Weiny
2025-02-06 18:33   ` Gregory Price
2025-02-07 17:54     ` Jonathan Cameron
2025-02-07 19:05     ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 06/16] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices Terry Bowman
2025-01-14 11:32   ` Jonathan Cameron
2025-01-14 20:44     ` Bowman, Terry
2025-01-28 20:25     ` Bowman, Terry
2025-01-29 18:04       ` Jonathan Cameron
2025-01-14 16:57   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 07/16] PCI/AER: Add CXL PCIe Port uncorrectable error recovery in AER service driver Terry Bowman
2025-01-14 11:33   ` Jonathan Cameron
2025-01-14 20:28     ` Bowman, Terry
2025-01-15 11:37       ` Jonathan Cameron
2025-01-14 17:27   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 08/16] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-01-14 21:37   ` Ira Weiny
2025-02-07  7:30   ` Gregory Price
2025-02-07 19:08     ` Bowman, Terry
2025-02-07 19:39       ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-01-14 11:35   ` Jonathan Cameron
2025-01-14 15:24     ` Bowman, Terry
2025-01-14 22:02   ` Ira Weiny
2025-01-14 22:11     ` Bowman, Terry
2025-01-14 23:38       ` Ira Weiny
2025-01-14 23:49         ` Bowman, Terry
2025-01-15 11:40           ` Jonathan Cameron
2025-02-07  7:35   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 10/16] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-01-14 11:39   ` Jonathan Cameron
2025-01-14 22:20   ` Ira Weiny
2025-02-07  7:38   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 11/16] cxl/pci: Add log message for umnapped registers in existing RAS handlers Terry Bowman
2025-01-14 11:41   ` Jonathan Cameron
2025-01-14 22:21   ` Ira Weiny
2025-02-07  7:39   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 12/16] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-01-14 22:23   ` Ira Weiny
2025-02-07  7:45     ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 13/16] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-01-14 11:46   ` Jonathan Cameron
2025-01-14 21:20     ` Bowman, Terry
2025-01-14 22:51   ` Ira Weiny
2025-01-14 23:10     ` Bowman, Terry
2025-01-14 23:42     ` Bowman, Terry
2025-02-07  8:01   ` Gregory Price
2025-02-07 19:23     ` Bowman, Terry
2025-02-07 19:41       ` Gregory Price
2025-02-07 21:04         ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 14/16] cxl/pci: Add trace logging " Terry Bowman
2025-01-14 11:49   ` Jonathan Cameron
2025-01-14 20:56     ` Bowman, Terry
2025-01-15 11:42       ` Jonathan Cameron
2025-01-14 22:58   ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 15/16] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-01-14 11:51   ` Jonathan Cameron
2025-01-14 23:03   ` Ira Weiny
2025-02-07  8:08   ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 16/16] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-01-14 23:26   ` Ira Weiny
2025-01-14 23:34     ` Bowman, Terry
2025-01-14 23:45       ` Ira Weiny
2025-01-15  0:09         ` Bowman, Terry
2025-01-15  0:20         ` Bowman, Terry
2025-01-16 21:42           ` Ira Weiny

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