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Wed, 15 Jan 2025 10:26:33 -0800 (PST) Received: from krava ([95.82.160.96]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9060db6sm791648366b.8.2025.01.15.10.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 10:26:33 -0800 (PST) From: Jiri Olsa X-Google-Original-From: Jiri Olsa Date: Wed, 15 Jan 2025 19:26:29 +0100 To: Steven Rostedt Cc: Jiri Olsa , Peter Zijlstra , Masami Hiramatsu , David Laight , lkml , linux-trace-kernel@vger.kernel.org, bpf@vger.kernel.org, x86@kernel.org Subject: Re: [RFC] x86/alternatives: Merge first and second step in text_poke_bp_batch Message-ID: References: <20250114140237.3506624-1-jolsa@kernel.org> <20250114141723.GS5388@noisy.programming.kicks-ass.net> <20250114103604.7388352c@gandalf.local.home> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250114103604.7388352c@gandalf.local.home> On Tue, Jan 14, 2025 at 10:36:04AM -0500, Steven Rostedt wrote: > On Tue, 14 Jan 2025 15:31:14 +0100 > Jiri Olsa wrote: > > > > IIRC this is the magic recipe blessed by both Intel and AMD, and > > > if we're going to be changing this I would want both vendors to sign off > > > on that. > > > > ok > > Right. In fact Intel wouldn't sign off on this recipe for a few years. We > actually added to the kernel before they gave their full blessing. I got a > "wink, it should work" from them but they wouldn't officially say so ;-) > > But a lot of it has to do with all the magic of the CPU. They have always > allowed writing the one byte int3. I figured, if I could write that one > byte int3 then run a sync on all CPUs where all CPUs see that change, then > nothing should ever care about the other 4 bytes after that int3 (a sync > was already done). Then change the 4 bytes and sync again. > > I doubt the int3 plus the 4 byte change would work, as was mentioned if the > other 4 bytes were on another cache line, another CPU could read the first > set of bytes without the int3 and the second set of bytes with the update > and go boom! > > This dance was to make sure everything sees everything properly. I gave a > talk about this at Kernel-Recipes in 2019: > > https://www.slideshare.net/slideshow/kernel-recipes-2019-ftrace-where-modifying-a-running-kernel-all-started/177509633#44 nice! thanks for all the details, jirka