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From: Sergey Matyukevich <geomatsi@gmail.com>
To: Christoph Hellwig <hch@lst.de>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: Re: [PATCH] riscv: select DMA_DIRECT_REMAP by RISCV_ISA_SVPBMT and ERRATA_THEAD_MAE
Date: Fri, 17 Jan 2025 14:01:41 +0300	[thread overview]
Message-ID: <Z4o4lVb_AUiQcvM5@curiosity> (raw)
In-Reply-To: <20250117095832.GB2585@lst.de>

Hi Christoph,

On Fri, Jan 17, 2025 at 10:58:32AM +0100, Christoph Hellwig wrote:
> On Fri, Jan 17, 2025 at 11:38:47AM +0300, Sergey Matyukevich wrote:
> > > Please explain what this is supposed to solve, because the above
> > > explanation dosn't make any sense.  DMA_DIRECT_REMAP is one
> > > of the implementations supporting dma coherent allocatiosn for
> > > non-coherent devices.  So selecting it from something that
> > > just keyes off support for an extension, but not the dma
> > > implementation is wrong.
> > 
> > Now DMA_DIRECT_REMAP is selected either by Zicbom (standard) or XTheadCmo
> > (vendor) RISC-V extensions.
> 
> Because they need DMA_DIRECT_REMAP to implement DMA coherent.
> 
> > However neither of them can help to implement
> > DMA_DIRECT_REMAP on RISC-V. So selection of DMA_DIRECT_REMAP has been
> > moved in Kconfigs to Svpbmt and XTheadMae extensions.
> 
> But Svpbmt does not imply that you even need DMA_DIRECT_REMAP.
> 
> Are you tying to solve a problem here?  If so can you explain it?

Sure. In brief, this about the choice between DMA_GLOBAL_POOL and
DMA_DIRECT_REMAP. We can use either of them to work with non-coherent
devices. But on RISC-V those two options require different extensions.

If we select DMA_GLOBAL_POOL, then we need only cache operations. So on
RISC-V it is enough to have Zicbom (standard) or XTheadCmo (vendor) or
any other vendor specific cache ops implemented using RISCV_ALTERNATIVE
or RISCV_NONSTANDARD_CACHE_OPS.

Using DMA_DIRECT_REMAP requires not only cache management operations,
but also a way to modify page attributes, e.g. to mark it non-cacheable. 
So on RISC-V in addition to CMO extensions we also need extensions for
page-based memory types such as Svpbmt (standard) or XTheadMae (vendor).

Current RISC-V Kconfig files enable DMA_DIRECT_REMAP for Zicbom and
XTheadCmo. According to the above comments, this is not good:
- it is wrong since Zicbom alone is not enough for DMA_DIRECT_REMAP
- it prevents using DMA_GLOBAL_POOL for platforms without support for
  page-based memory attributes

My suggestion was to move DMA_DIRECT_REMAP to the Kconfig entries for
Svpbmt and XTheadMae. In this case platforms without Svpbmt support
can disable it in kernel config and switch to DMA_GLOBAL_POOL instead.

IIUC one of your concerns was selecting DMA_DIRECT_REMAP under config
option not related to DMA implementations. Does it make sense to add
additional layer similar to RISCV_DMA_NONCOHERENT ?

Regards,
Sergey

  reply	other threads:[~2025-01-17 11:01 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16 17:29 [PATCH] riscv: select DMA_DIRECT_REMAP by RISCV_ISA_SVPBMT and ERRATA_THEAD_MAE Sergey Matyukevich
2025-01-17  7:52 ` Christoph Hellwig
2025-01-17  8:38   ` Sergey Matyukevich
2025-01-17  9:58     ` Christoph Hellwig
2025-01-17 11:01       ` Sergey Matyukevich [this message]
2025-02-17 12:23 ` Alexandre Ghiti
2025-02-20  9:48   ` Sergey Matyukevich
2025-02-26 13:58     ` Alexandre Ghiti

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