From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D16B72AF16 for ; Fri, 17 Jan 2025 14:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737124266; cv=none; b=Wi8OyidEJdYKTQ/JrzqdVTFFZiSj3q5P6gOaHZM7fa/4fAu34XoR3a8VyaDsucAwnL/FBJMyEVG9IVYzIxwv92QI+XcyVjG3SVsyTYwdy00BYJoo3lis5i49+yjvyNgLnuktfyImYswR3cq57rb5Xj34AEa3COU0mjAZGzFoIwM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737124266; c=relaxed/simple; bh=WBY7QKi2b3acbB15Gt/cmPsoC4QFmjHRmgXYYdRWeAg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jj8vqImsYy6ABremwbyWskjFpagoUGTSHQOb6QWodNBtyI95TP6pH9LpbE3SQiSrSmgMaOEX+otAopmsQULuZEC1dg4PSAxc32vJovCOqMManqrK8k6YNKGTs0YfzyZZD1k/MwtmpeYXcMT4bUTS9Iwci5DkWL4kb9cpEEJGX8Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KV426Klj; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KV426Klj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737124265; x=1768660265; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=WBY7QKi2b3acbB15Gt/cmPsoC4QFmjHRmgXYYdRWeAg=; b=KV426KljyO0e8iIW9LXa22gM4DBJ0qovbrm8HZWVxuUwcEgEg6HUsgnY bgym/rE0gMrUjzTcLkILOBc64B8e7pzc53uTRHe70mpBoSF6kNi2hAEuz 10oXD6RO3eMGGQmEq4tCML0paKqioHl35+RI3m9G+7VPyBJhE0uS+NeXF 1JKNATNKMabaRsgRg6F5JhhZJqFY1jcUy2EsKAiHGntxCDPe5nvcJwd7e kAY2JuM3Xz3b/ZyCXnC2q2uXWahEfEtU3DsSRAg5hQpgurvfaNHh3Nqsg aDt8n8VOKh2Dw2G3ukmeA66+G51F+E0X+CM8X75+ShhFofGuO+eL2vjCz w==; X-CSE-ConnectionGUID: 7PK2FLtwQlu5zDQs7PFcPQ== X-CSE-MsgGUID: obO/Yeb6Sr+eHYBRrJ6Odw== X-IronPort-AV: E=McAfee;i="6700,10204,11318"; a="37437658" X-IronPort-AV: E=Sophos;i="6.13,212,1732608000"; d="scan'208";a="37437658" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:31:04 -0800 X-CSE-ConnectionGUID: hKLQh85bRXCTbBmbmVZ1xA== X-CSE-MsgGUID: P2psl3lhT4WCxmM025Q1Yw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="106283938" Received: from unknown (HELO smile.fi.intel.com) ([10.237.72.154]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2025 06:31:03 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.98) (envelope-from ) id 1tYnND-000000025gp-1ohT; Fri, 17 Jan 2025 16:30:59 +0200 Date: Fri, 17 Jan 2025 16:30:59 +0200 From: Andy Shevchenko To: Marek Szyprowski Cc: Mark Brown , linux-kernel@vger.kernel.org, Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Dmitry Baryshkov , DRI mailing list Subject: Re: [PATCH v3 1/1] regmap: Synchronize cache for the page selector Message-ID: References: <20250116124303.3941583-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Fri, Jan 17, 2025 at 04:09:58PM +0200, Andy Shevchenko wrote: > On Fri, Jan 17, 2025 at 02:57:52PM +0100, Marek Szyprowski wrote: > > On 16.01.2025 13:42, Andy Shevchenko wrote: > > > If the selector register is represented in each page, its value > > > in accordance to the debugfs is stale because it gets synchronized > > > only after the real page switch happens. Synchronize cache for > > > the page selector. > > > > > > Before (offset followed by hexdump, the first byte is selector): > > > > > > // Real registers > > > 18: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > ... > > > // Virtual (per port) > > > 40: 05 ff 00 00 e0 e0 00 00 00 00 00 1f > > > 50: 00 ff 00 00 e0 e0 00 00 00 00 00 1f > > > 60: 01 ff 00 00 ff ff 00 00 00 00 00 00 > > > 70: 02 ff 00 00 cf f3 00 00 00 00 00 0c > > > 80: 03 ff 00 00 00 00 00 00 00 00 00 ff > > > 90: 04 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > > > > After: > > > > > > // Real registers > > > 18: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > ... > > > // Virtual (per port) > > > 40: 00 ff 00 00 e0 e0 00 00 00 00 00 1f > > > 50: 01 ff 00 00 e0 e0 00 00 00 00 00 1f > > > 60: 02 ff 00 00 ff ff 00 00 00 00 00 00 > > > 70: 03 ff 00 00 cf f3 00 00 00 00 00 0c > > > 80: 04 ff 00 00 00 00 00 00 00 00 00 ff > > > 90: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > > > > Fixes: 6863ca622759 ("regmap: Add support for register indirect addressing.") > > > Signed-off-by: Andy Shevchenko > > > > This patch landed in linux-next some time ago as commit 1fd60ed1700c > > ("regmap: Synchronize cache for the page selector"). Today I've noticed > > that it causes a regression for Lontium LT9611UXC HDMI bridge driver. > > Is there any datasheet link to the HW in question? > > (FWIW, I have tested this with the CY8C9540 GPIO I˛C expander on Intel Galileo > Gen 1 board.) > > > With today's linux-next I got the following messages on QCom RB5 board: > > > > # dmesg | grep  lt9611uxc > > [   13.737346] lt9611uxc 5-002b: LT9611 revision: 0x00.00.00 > > [   13.804190] lt9611uxc 5-002b: LT9611 version: 0x00 > > [   13.870564] lt9611uxc 5-002b: FW version 0, enforcing firmware update > > [   13.877437] lt9611uxc 5-002b: Direct firmware load for > > lt9611uxc_fw.bin failed with error -2 > > [   13.887517] lt9611uxc 5-002b: probe with driver lt9611uxc failed with > > error -2 > > > > after reverting the $subject patch, the driver probes fine on that board. > > > > I'm not sure if this is really a bug caused by this change or simply the > > driver already was aligned to old regmap behavior. Dmitry, could you > > check the regamp usage and review the changes introduced by this patch? > > Let me know if there is anything to check on the real hardware to help > > resolving this issue. > > Yes, see below. And thank you for your report! > > ... > > > > + /* > > > + * If selector register has been just updated, update the respective > > > + * virtual copy as well. > > > + */ > > > + if (page_chg && > > > + in_range(range->selector_reg, range->window_start, range->window_len)) > > > + _regmap_update_bits(map, sel_register, mask, val, NULL, false); > > Can you add a test printk() here to show > > page_chg > range->selector_reg, range->window_start, range->window_len > sel_register, mask, val > > ? > > And would commenting these three lines make it work again? Also try to apply this patch (while having the above lines not commented): >From 0fe5fe51d8b86305a4ca1ae44ede34a24fe2f9d7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 17 Jan 2025 16:29:19 +0200 Subject: [PATCH 1/1] TBD: Signed-off-by: Andy Shevchenko --- drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index f4c3ff1fdc69..35a1dd568bbb 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -69,7 +69,7 @@ struct lt9611uxc { static const struct regmap_range_cfg lt9611uxc_ranges[] = { { .name = "register_range", - .range_min = 0, + .range_min = 0x0100, .range_max = 0xd0ff, .selector_reg = LT9611_PAGE_CONTROL, .selector_mask = 0xff, -- 2.43.0.rc1.1336.g36b5255a03ac -- With Best Regards, Andy Shevchenko