From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C4748F7D for ; Wed, 22 Jan 2025 21:02:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737579748; cv=none; b=hRDxBRFbU3rU+3kDtxlctm+M7gfXQIAmXbUAS27VbWdCftzj0wn1nzsgGnWOVGPRQvfu0AZa8KAdSO5kj4urbzgKVj4F9eB4oEwG0AN088wbeSTl8uKJZ0JsdS4l1tuSoYrVtJkjbDbi7d+ccmH4tZlyZkCdM9HAipSgyZ9LtTM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737579748; c=relaxed/simple; bh=pLJ/MLuvuagw10c9IniFm4CuSVxD8IIYNjKXFFggoho=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=GDdenC01xxbbMV+KYmSNcbwtX3MtXpU9sYhO00z5VVEvDoIaOxrvF3gBVAx69j1Qm7n/tn47HLNB/4VPK0wXrWLthRSJplevwLtpN4hAqrqfLXCMxsIJwJv/Pw7xlE3MNGml/4UeJ9KH1gT9p8SfVj4yOy6h22jueSudYTqIVgI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mlP7w1nf; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mlP7w1nf" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-2161d185f04so1652665ad.3 for ; Wed, 22 Jan 2025 13:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1737579746; x=1738184546; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DicZYtp/EHieoQvK3C/2OykVBIHxoy6pTrroBeARA8Q=; b=mlP7w1nfiaZemmmx2+HiFBRRkL8AbOC/9KbZI5W64SrOHIvP+c1geZJwmfEZ8OfK4c 1RdZ7aJDD+lQFDzKbqudkyOhx8Zu8s2sStpQdPcTVtaIZr4TOPSEJyGP0hnpBQIoQe+l 3wJ2fuHg+xTN4BTzqw5ksdmOxLhWt8aIqp9xc2xgVDuVIsz/G3sZmWowWY6Y0emRdAwR B8Y1LKMueNLoJqFhxu/olssVmN3G6YG0Cx1N23OOre5vjyyG1ewdv9+hIIe0Z+hQ88qu M/3BtKBeSuSoaufbEyGtW2whTP1RnlgROcnnBjz3YBrjd/31jdnNK2SoRuEmmDKHWXkZ FvMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737579746; x=1738184546; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DicZYtp/EHieoQvK3C/2OykVBIHxoy6pTrroBeARA8Q=; b=F8we2Oy9gaECgpE2IugsTRQgh9UmVNCEkJaBSiIkScRg8fMpdSwVN1YL4tNp60WxFd l7vfJ82EYEqJj/u3Sy6jcM9srFczXc4GnXHbzVxLNPUTdWiJ9A3+D2F62QQXxEXA5C1s 95Fg1Q4+G0gmQ8MnrXSCXV6nL+7u3aGfxdzoDhOGshP2YzbhoWUotGVjLHd9mi/917Dv 1kTZCvHCm0NPvzuKyM2cele+9t+EFk02jrcaCkOFXflFTx4fNBk0UW+BbLMkcBg5/j30 Ro0M7oz41QM85pWBOQllEDP3tiL/4SjURSxZId35lzISBOZihDy3x5VjSGQotIYCjW2s 0TyA== X-Forwarded-Encrypted: i=1; AJvYcCUq+81u8z4kmcxwjCxWBclxRBUNI5ByAIZso/qN+pxVL06CeWgTbvmHrHQAThsxUszu3med6o5zLO/6iNU=@vger.kernel.org X-Gm-Message-State: AOJu0YzRRHW4kyByTikxZm67AtlzqINH5Zb+b4dkX5HOKb372YxDJBDw AiN8f53o7qhoCEMFTobIPUZnOK/nnSzXGF38vA7ppMXVfc/B37LC8D6ty5v1Gi1xbF+h55EPeC8 KKw== X-Google-Smtp-Source: AGHT+IHM2QebG58cNXyhzFMVNZ1kenC/xYWAhyilKflk6S5aKuHiubU8xjxlTDSIV8gXkbMieHxUCIPeVME= X-Received: from pgbck6.prod.google.com ([2002:a05:6a02:906:b0:8ae:4cf4:372]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:789a:b0:1e6:51d2:c8e3 with SMTP id adf61e73a8af0-1eb215f52a7mr44525602637.35.1737579746710; Wed, 22 Jan 2025 13:02:26 -0800 (PST) Date: Wed, 22 Jan 2025 13:02:25 -0800 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <948408887cbe83cbcf05452a53d33fb5aaf79524.camel@redhat.com> Message-ID: Subject: Re: vmx_pmu_caps_test fails on Skylake based CPUS due to read only LBRs From: Sean Christopherson To: Maxim Levitsky Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Wed, Jan 22, 2025, Maxim Levitsky wrote: > On Tue, 2025-01-21 at 17:02 -0800, Sean Christopherson wrote: > > On Sun, Nov 03, 2024, Maxim Levitsky wrote: > > > On Mon, 2024-10-28 at 08:55 -0700, Sean Christopherson wrote: > > > > On Fri, Oct 18, 2024, Maxim Levitsky wrote: > > > > > Our CI found another issue, this time with vmx_pmu_caps_test. > > > > > > > > > > On 'Intel(R) Xeon(R) Gold 6328HL CPU' I see that all LBR msrs (from/to and > > > > > TOS), are always read only - even when LBR is disabled - once I disable the > > > > > feature in DEBUG_CTL, all LBR msrs reset to 0, and you can't change their > > > > > value manually. Freeze LBRS on PMI seems not to affect this behavior. > > > > ... > > > > > When DEBUG_CTL.LBR=1, the LBRs do work, I see all the registers update, > > > although TOS does seem to be stuck at one value, but it does change > > > sometimes, and it's non zero. > > > > > > The FROM/TO do show healthy amount of updates > > > > > > Note that I read all msrs using 'rdmsr' userspace tool. > > > > I'm pretty sure debugging via 'rdmsr', i.e. /dev/msr, isn't going to work. I > > assume perf is clobbering LBR MSRs on context switch, but I haven't tracked that > > down to confirm (the code I see on inspecition is gated on at least one perf > > event using LBRs). My guess is that there's a software bug somewhere in the > > perf/KVM exchange. > > > > I confirmed that using 'rdmsr' and 'wrmsr' "loses" values, but that hacking KVM > > to read/write all LBRs during initialization works with LBRs disabled. > > Hi, > > OK, this is a very good piece of the puzzle. > > I didn't expect context switch to interfere with this because I thought that > perf code won't touch LBRs if they are not in use. > rdmsr/wrmsr programs don't do much except doing the instruction in the kernel space. > > Is it then possible that the the fact that LBRs were left enabled by BIOS is the > culprit of the problem? > > This particular test never enables LBRs, not anything in the system does this, Ugh, but it does. On writes to any LBR, including LBR_TOS, KVM creates a "virtual" LBR perf event. KVM then relies on perf to context switch LBR MSRs, i.e. relies on perf to load the guest's values into hardware. At least, I think that's what is supposed to happen. AFAIK, the perf-based LBR support has never been properly document[*]. Anyways, my understanding of intel_pmu_handle_lbr_msrs_access() is that if the vCPU's LBR perf event is scheduled out or can't be created, the guest's value is effectively lost. Again, I don't know the "rules" for the LBR perf event, but it wouldn't suprise me if your CI fails because something in the host conflicts with KVM's LBR perf event. [*] https://lore.kernel.org/all/Y9RUOvJ5dkCU9J8C@google.com