From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D5AF199EAF for ; Tue, 28 Jan 2025 20:54:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738097683; cv=none; b=uH4bb5GSlhw1AD4nwKXmOKCAFii96YuLABEDyEccK9V/CQx8DKHabozLq68qWD64qzzmKIZrZovnHoM36t6JbEguJB/flO2Nbg7GwHBrqJrMQrvWHK9uRiLyQholCYm/goFCwuZWut6wuEDvKl9Ir1H1qbVDHJcIucK4OUF8ML8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738097683; c=relaxed/simple; bh=h8u0HLcNpQuOyHmdjLiUpwxLCaRl9ymGV5khS2Np4rA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=IcLTUug/vXbHzeHlxWhHthpzpC+IYGwMIuivSWNXQSKi2WrcV1SAu1HUd5B9YxzugnXxyodHObLpQoPEOSZT3ofwknEMz6DNJ7Sso6HqYX5izGbx0KvSL1oHMexVHiwTekrUH5rt/n2ZZcl96pwJel7JJRRtGVAtL9NcCoNSlwI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=BbS7v2kS; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="BbS7v2kS" Date: Tue, 28 Jan 2025 12:54:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1738097679; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Aggod8/in0cKWs0kG+tFQuM++ochnefqccqd7dtFIgs=; b=BbS7v2kSahLi5d25+Z69i5JoQCAP7OvkfyTzOF7QqSM3a1LJPWaUbGnd5BOgOQYTxYIe4p jdYl7295TiVmYC7jZLhheMifHAOv0ZuiW0nWl+VdqgYmTQwf6c5J0Cq8ckZSP/ZQr+CV4P +ECaLlYzWSVbms3v5jOiZQmrJhBaZ5c= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: Zaid Alali , catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com, ruanjinjie@huawei.com, robh@kernel.org, anshuman.khandual@arm.com, james.morse@arm.com, shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com, scott@os.amperecomputing.com, joey.gouly@arm.com, ardb@kernel.org, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative Message-ID: References: <20250127201829.209258-1-zaidal@os.amperecomputing.com> <87msfbtjyw.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87msfbtjyw.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT On Tue, Jan 28, 2025 at 08:34:47AM +0000, Marc Zyngier wrote: > > +config AMPERE_ERRATUM_AC03_CPU_50 > > + bool "AmpereOne: AC03_CPU_50: Certain checks for ICC_PMR_EL1 that expects the value 0xf0 may read 0xf8 instead" > > + default y > > + help > > + This option adds an alternative code sequence to work around Ampere > > + erratum AC03_CPU_50 on AmpereOne and Ampere1A. > > + > > + Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a > > + direct read of the register will return a value of 0xf8. An incorrect > > + value from a direct read can only happen with the value 0xf0. > > + > > + The workaround for the erratum will do logical AND 0xf0 to the > > + value read from ICC_PMR_EL1 register before returning the value. > > + > > + If unsure, say Y. > > + > > An alternative for this would simply to prevent the enabling of pNMI > on this platform. There's also AC03_CPU_36, where the CPU goes into the weeds if you take an asynchronous exception while fiddling with HCR_EL2. We don't have a mitigation for it, and it can be pretty easily reproduced by using pNMIs while running VMs. So I agree, disabling pNMIs might be the easier way out. [*] https://amperecomputing.com/assets/AmpereOne_Developer_ER_v0_80_20240823_28945022f4.pdf -- Thanks, Oliver