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Message-ID: References: <20250129131703.733098-1-arikalo@gmail.com> <20250129-museum-slider-3bb634d124de@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250129-museum-slider-3bb634d124de@spud> On Wed, Jan 29, 2025 at 04:19:58PM +0000, Conor Dooley wrote: > On Wed, Jan 29, 2025 at 02:17:03PM +0100, Aleksandar Rikalo wrote: > > From: Djordje Todorovic > > > > The riscv MIPS P8700 uses a different opcode for PAUSE. > > It is a ‘hint’ encoding of the SLLI instruction, with rd=0, rs1=0 and > > imm=5. It will behave as a NOP instruction if no additional behavior > > beyond that of SLLI is implemented. > > You say p8700, but the erratum will be applied on all systems that are > identified as using a mips cpu. Why's that? > > > +void mips_errata_patch_func(struct alt_entry *begin, > > + struct alt_entry *end, > > + unsigned long archid, > > + unsigned long impid, > > + unsigned int stage) > > +{ > > + struct alt_entry *alt; > > + > > + BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE); > > + > > + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) > > + return; > > + > > + for (alt = begin; alt < end; alt++) { > > + if (alt->vendor_id != MIPS_VENDOR_ID) > > + continue; > > + > > + if (alt->patch_id >= ERRATA_MIPS_NUMBER) { > > + WARN(1, "MIPS errata id:%d not in kernel errata list\n", > > + alt->patch_id); > > + continue; > > + } > > + > > + mutex_lock(&text_mutex); > > + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), alt->alt_len); > > + mutex_unlock(&text_mutex); > > + } > > +} > > > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h > > index 662aca039848..880f26a24f69 100644 > > --- a/tools/arch/riscv/include/asm/vdso/processor.h > > +++ b/tools/arch/riscv/include/asm/vdso/processor.h > > @@ -14,7 +14,10 @@ static inline void cpu_relax(void) > > __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > > #endif > > > > -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > > +#ifdef CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE > > + /* MIPS P8700 pause opcode */ > > + __asm__ __volatile__ (".4byte 0x00501013"); > > +#elif CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > > /* > > * Reduce instruction retirement. > > * This assumes the PC changes. > > What about when the erratum is enabled and the toolchain supports > Zihintpause? So the other way to do this is having an hwprobe call to check if the currently running processor is effected by this. However I was concerned about the performance penalty of calling hwprobe here in the previous version so I had suggested to use a flag instead so there is not the penalty on other architectures. This does make it invalid to enable this errata in the defconfig. This is a precedent for how we want to handle errata in tools. > Why don't you use the same implementation as the !tools > copy of the header? (I'm not sure why they're different in the first > place). It is different because the headers in tools are userspace so it doesn't make sense to have alternatives. - Charlie > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv