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An incorrect > > > + value from a direct read can only happen with the value 0xf0. > > > + > > > + The workaround for the erratum will do logical AND 0xf0 to the > > > + value read from ICC_PMR_EL1 register before returning the value. > > > + > > > + If unsure, say Y. > > > + > > > > An alternative for this would simply to prevent the enabling of pNMI > > on this platform. > > There's also AC03_CPU_36, where the CPU goes into the weeds if you take > an asynchronous exception while fiddling with HCR_EL2. We don't have a > mitigation for it, and it can be pretty easily reproduced by using pNMIs > while running VMs. > > So I agree, disabling pNMIs might be the easier way out. > > [*] https://amperecomputing.com/assets/AmpereOne_Developer_ER_v0_80_20240823_28945022f4.pdf > We prefer to keep pNMIs enabled if possible since it is useful, and we will send another patch for AC03_CPU_36 to fix that. If this is not feasible we can send another patch to disable it in both AC03_CPU_36 and AC03_CPU_50. > -- > Thanks, > Oliver