From: Gregory Price <gourry@gourry.net>
To: Terry Bowman <terry.bowman@amd.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com,
oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com,
nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
lukas@wunner.de, ming.li@zohomail.com,
PradeepVineshReddy.Kodamati@amd.com, alucerop@amd.com
Subject: Re: [PATCH v5 02/16] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support
Date: Thu, 6 Feb 2025 12:02:36 -0500 [thread overview]
Message-ID: <Z6TrLKCthMY9g24W@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250107143852.3692571-3-terry.bowman@amd.com>
On Tue, Jan 07, 2025 at 08:38:38AM -0600, Terry Bowman wrote:
> The AER service driver already includes support for Restricted CXL host
> (RCH) Downstream Port Protocol Error handling. The current implementation
> is based on CXL1.1 using a Root Complex Event Collector.
>
> Rename function interfaces and parameters where necessary to include
> virtual hierarchy (VH) mode CXL PCIe Port error handling alongside the RCH
> handling.[1] The CXL PCIe Port Protocol Error handling support will be
> added in a future patch.
>
> Limit changes to renaming variable and function names. No functional
> changes are added.
>
> [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
next prev parent reply other threads:[~2025-02-06 17:02 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 14:38 [PATCH v5 0/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-01-07 14:38 ` [PATCH v5 01/16] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-01-13 23:45 ` Ira Weiny
2025-02-06 17:01 ` Gregory Price
2025-02-07 18:35 ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 02/16] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-01-13 23:45 ` Ira Weiny
2025-02-06 17:02 ` Gregory Price [this message]
2025-01-07 14:38 ` [PATCH v5 03/16] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-01-13 23:49 ` Ira Weiny
2025-01-14 15:19 ` Bowman, Terry
2025-01-14 23:33 ` Ira Weiny
2025-01-14 23:39 ` Bowman, Terry
2025-01-16 15:35 ` Ira Weiny
2025-01-15 10:03 ` Lukas Wunner
2025-01-07 14:38 ` [PATCH v5 04/16] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-01-13 23:51 ` Ira Weiny
2025-02-06 18:18 ` Gregory Price
2025-02-07 18:50 ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 05/16] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-01-14 6:54 ` Li Ming
2025-01-14 11:20 ` Jonathan Cameron
2025-01-14 20:10 ` Bowman, Terry
2025-01-14 19:29 ` Bowman, Terry
2025-01-15 1:18 ` Li Ming
2025-01-15 14:39 ` Bowman, Terry
2025-01-16 3:15 ` Li Ming
2025-02-05 3:46 ` Bowman, Terry
2025-02-05 13:58 ` Li Ming
2025-02-05 14:22 ` Bowman, Terry
2025-01-14 16:35 ` Ira Weiny
2025-02-06 18:33 ` Gregory Price
2025-02-07 17:54 ` Jonathan Cameron
2025-02-07 19:05 ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 06/16] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices Terry Bowman
2025-01-14 11:32 ` Jonathan Cameron
2025-01-14 20:44 ` Bowman, Terry
2025-01-28 20:25 ` Bowman, Terry
2025-01-29 18:04 ` Jonathan Cameron
2025-01-14 16:57 ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 07/16] PCI/AER: Add CXL PCIe Port uncorrectable error recovery in AER service driver Terry Bowman
2025-01-14 11:33 ` Jonathan Cameron
2025-01-14 20:28 ` Bowman, Terry
2025-01-15 11:37 ` Jonathan Cameron
2025-01-14 17:27 ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 08/16] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-01-14 21:37 ` Ira Weiny
2025-02-07 7:30 ` Gregory Price
2025-02-07 19:08 ` Bowman, Terry
2025-02-07 19:39 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-01-14 11:35 ` Jonathan Cameron
2025-01-14 15:24 ` Bowman, Terry
2025-01-14 22:02 ` Ira Weiny
2025-01-14 22:11 ` Bowman, Terry
2025-01-14 23:38 ` Ira Weiny
2025-01-14 23:49 ` Bowman, Terry
2025-01-15 11:40 ` Jonathan Cameron
2025-02-07 7:35 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 10/16] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-01-14 11:39 ` Jonathan Cameron
2025-01-14 22:20 ` Ira Weiny
2025-02-07 7:38 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 11/16] cxl/pci: Add log message for umnapped registers in existing RAS handlers Terry Bowman
2025-01-14 11:41 ` Jonathan Cameron
2025-01-14 22:21 ` Ira Weiny
2025-02-07 7:39 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 12/16] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-01-14 22:23 ` Ira Weiny
2025-02-07 7:45 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 13/16] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-01-14 11:46 ` Jonathan Cameron
2025-01-14 21:20 ` Bowman, Terry
2025-01-14 22:51 ` Ira Weiny
2025-01-14 23:10 ` Bowman, Terry
2025-01-14 23:42 ` Bowman, Terry
2025-02-07 8:01 ` Gregory Price
2025-02-07 19:23 ` Bowman, Terry
2025-02-07 19:41 ` Gregory Price
2025-02-07 21:04 ` Bowman, Terry
2025-01-07 14:38 ` [PATCH v5 14/16] cxl/pci: Add trace logging " Terry Bowman
2025-01-14 11:49 ` Jonathan Cameron
2025-01-14 20:56 ` Bowman, Terry
2025-01-15 11:42 ` Jonathan Cameron
2025-01-14 22:58 ` Ira Weiny
2025-01-07 14:38 ` [PATCH v5 15/16] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-01-14 11:51 ` Jonathan Cameron
2025-01-14 23:03 ` Ira Weiny
2025-02-07 8:08 ` Gregory Price
2025-01-07 14:38 ` [PATCH v5 16/16] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-01-14 23:26 ` Ira Weiny
2025-01-14 23:34 ` Bowman, Terry
2025-01-14 23:45 ` Ira Weiny
2025-01-15 0:09 ` Bowman, Terry
2025-01-15 0:20 ` Bowman, Terry
2025-01-16 21:42 ` Ira Weiny
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