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[34.16.141.147]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ad51af64c1dsm6573311a12.52.2025.02.09.15.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 15:42:02 -0800 (PST) Date: Sun, 9 Feb 2025 23:41:56 +0000 From: Peilin Ye To: Alexei Starovoitov Cc: bpf , linux-arm-kernel , bpf@ietf.org, Xu Kuohai , Eduard Zingerman , David Vernet , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Jonathan Corbet , "Paul E. McKenney" , Puranjay Mohan , Ilya Leoshkevich , Heiko Carstens , Vasily Gorbik , Catalin Marinas , Will Deacon , Quentin Monnet , Mykola Lysenko , Shuah Khan , Ihor Solodrai , Yingchi Long , Josh Don , Barret Rhoden , Neel Natu , Benjamin Segall , LKML Subject: Re: [PATCH bpf-next v2 4/9] bpf: Introduce load-acquire and store-release instructions Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Sat, Feb 08, 2025 at 07:46:54PM -0800, Alexei Starovoitov wrote: > > > These values might imply that bpf infra is supposed to map all the values > > > to cpu instructions, but that's not what we're doing here. > > > We're only dealing with two specific instructions. > > > We're not defining a memory model for all future new instructions. > > > > Got it! In v3, I'll change it back to: > > > > #define BPF_LOAD_ACQ 0x10 > > #define BPF_STORE_REL 0x20 > > why not 1 and 2 ? > All other bits are reserved and the verifier will make sure they're zero, > so when/if we need to extend it then it wouldn't matter whether > lower 4 bits are reserved or other bits. > Say, we decide to support cmpwait_relaxed as a new insn. > It can take the value 3 and arm64 JIT will map it to ldxr+wfe+... > > Then with this new load_acq and cmpwait_relaxed we can efficiently > implement both smp_cond_load_relaxed and smp_cond_load_acquire. Ah, I see. When you suggested "LOAD_ACQ=1 and STORE_REL=2" earlier, I didn't realize you meant 1 and 2 in imm<0-3>. Thanks, Peilin Ye