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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c065424c9esm257293885a.43.2025.02.11.16.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 16:11:24 -0800 (PST) Date: Tue, 11 Feb 2025 19:11:21 -0500 From: Gregory Price To: Terry Bowman Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com Subject: Re: [PATCH v7 13/17] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Message-ID: References: <20250211192444.2292833-1-terry.bowman@amd.com> <20250211192444.2292833-14-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250211192444.2292833-14-terry.bowman@amd.com> On Tue, Feb 11, 2025 at 01:24:40PM -0600, Terry Bowman wrote: > The CXL drivers use kernel trace functions for logging Endpoint and > Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality > is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL > Upstream Switch Ports. > > Introduce trace logging functions for both RAS correctable and > uncorrectable errors specific to CXL PCIe Ports. Additionally, update > the CXL Port Protocol Error handlers to invoke these new trace functions. > > Examples of the output from these changes is below. > > Correctable error: > cxl_port_aer_correctable_error: device=port1 parent=root0 status='Received Error From Physical Layer' > > Uncorrectable error: > cxl_port_aer_uncorrectable_error: device=port1 parent=root0 status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Erro' > > Signed-off-by: Terry Bowman > Reviewed-by: Alejandro Lucero > Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price