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[34.16.141.147]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7324273e318sm4272875b3a.96.2025.02.14.22.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2025 22:17:29 -0800 (PST) Date: Sat, 15 Feb 2025 06:17:21 +0000 From: Peilin Ye To: Alexei Starovoitov Cc: bpf , linux-arm-kernel , bpf@ietf.org, Xu Kuohai , Eduard Zingerman , David Vernet , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Jonathan Corbet , "Paul E. McKenney" , Puranjay Mohan , Ilya Leoshkevich , Heiko Carstens , Vasily Gorbik , Catalin Marinas , Will Deacon , Quentin Monnet , Mykola Lysenko , Shuah Khan , Ihor Solodrai , Yingchi Long , Josh Don , Barret Rhoden , Neel Natu , Benjamin Segall , LKML Subject: Re: [PATCH bpf-next v2 4/9] bpf: Introduce load-acquire and store-release instructions Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Feb 14, 2025 at 07:04:13PM -0800, Alexei Starovoitov wrote: > > > > How about: > > > > #define BPF_LOAD_ACQ 2 > > > > #define BPF_STORE_REL 3 > > > > > > > > and only use them with BPF_MOV like > > > > > > > > imm = BPF_MOV | BPF_LOAD_ACQ - is actual load acquire > > > > imm = BPF_MOV | BPF_STORE_REL - release > > > > Based on everything discussed, should we proceed with the above > > suggestion? Specifically: > > > > #define BPF_LD_ST BPF_MOV /* 0xb0 */ > > The aliasing still bothers me. > I hated doing it when going from cBPF to eBPF, > but we only had 8-bit to work with. > Here we have 32-bit. > Aliases make disassemblers trickier, since value no longer > translates to string as-is. It depends on the context. > There is probably no use for BPF_MOV operation in atomic > context, but by reusing BPF_ADD, BPF_XOR, etc in atomic > we signed up ourselves for all of alu ops. I see. > That's why BPF_XCHG and BPF_CMPXCHG are outside > of alu op range. > > So my preference is to do: > #define BPF_LOAD_ACQ 0x100 > #define BPF_STORE_REL 0x110 > #define BPF_CMPWAIT_RELAXED 0x120 > > and keep growing it. > We burn the first nibble, but so be it. Got it! In instruction-set.rst I'll make it clear that imm<0-3> must be zero for load_acq/store_rel. Cheers, Peilin Ye