From: Nicolin Chen <nicolinc@nvidia.com>
To: Baolu Lu <baolu.lu@linux.intel.com>
Cc: <jgg@nvidia.com>, <kevin.tian@intel.com>, <robin.murphy@arm.com>,
<joro@8bytes.org>, <will@kernel.org>, <iommu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/4] iommu: Add private_data_owner to iommu_domain
Date: Thu, 27 Feb 2025 19:23:35 -0800 [thread overview]
Message-ID: <Z8EsN/Vg2SVeChTp@Asurada-Nvidia> (raw)
In-Reply-To: <f6d0fcb1-b974-440f-9208-257422bc01a6@linux.intel.com>
On Fri, Feb 28, 2025 at 11:13:23AM +0800, Baolu Lu wrote:
> On 2/28/25 09:31, Nicolin Chen wrote:
> > Steal two bits from the 32-bit "type" in struct iommu_domain to store a
> > new tag for private data owned by either dma-iommu or iommufd.
> >
> > Set the domain->private_data_owner in dma-iommu and iommufd. These will
> > be used to replace the sw_msi function pointer.
> >
> > Suggested-by: Jason Gunthorpe<jgg@nvidia.com>
> > Signed-off-by: Nicolin Chen<nicolinc@nvidia.com>
> > ---
> > include/linux/iommu.h | 7 ++++++-
> > drivers/iommu/dma-iommu.c | 2 ++
> > drivers/iommu/iommufd/hw_pagetable.c | 3 +++
> > 3 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> > index e93d2e918599..4f2774c08262 100644
> > --- a/include/linux/iommu.h
> > +++ b/include/linux/iommu.h
> > @@ -209,8 +209,13 @@ struct iommu_domain_geometry {
> > #define IOMMU_DOMAIN_PLATFORM (__IOMMU_DOMAIN_PLATFORM)
> > #define IOMMU_DOMAIN_NESTED (__IOMMU_DOMAIN_NESTED)
> > +#define IOMMU_DOMAIN_DATA_OWNER_NONE (0U)
> > +#define IOMMU_DOMAIN_DATA_OWNER_DMA (1U)
> > +#define IOMMU_DOMAIN_DATA_OWNER_IOMMUFD (2U)
> > +
> > struct iommu_domain {
> > - unsigned type;
> > + u32 type : 30;
> > + u32 private_data_owner : 2;
>
> Is there any special consideration for reserving only 2 bits for the
> private data owner? Is it possible to allocate more bits so that it
> could be more extensible for the future?
It could. This "2" is copied from Jason's suggestion:
https://lore.kernel.org/linux-iommu/20250227194749.GJ39591@nvidia.com/
> For example, current iommu core allows a kernel device driver to
> allocate a paging domain and replace the default domain for kernel DMA.
> This suggests the private data owner bits may be needed beyond iommu-dma
> and iommufd.
What's the potential "private data" in this case?
Thanks
Nicolin
next prev parent reply other threads:[~2025-02-28 3:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 1:31 [PATCH v2 0/4] iommu: Isolate iova_cookie to actual owners Nicolin Chen
2025-02-28 1:31 ` [PATCH v2 1/4] iommu: Add private_data_owner to iommu_domain Nicolin Chen
2025-02-28 3:13 ` Baolu Lu
2025-02-28 3:23 ` Nicolin Chen [this message]
2025-02-28 3:29 ` Baolu Lu
2025-02-28 16:29 ` Robin Murphy
2025-02-28 17:40 ` Nicolin Chen
2025-02-28 1:31 ` [PATCH v2 2/4] iommufd: Move iommufd_sw_msi and related functions to driver.c Nicolin Chen
2025-02-28 17:32 ` Jason Gunthorpe
2025-02-28 17:54 ` Nicolin Chen
2025-02-28 18:02 ` Jason Gunthorpe
2025-02-28 18:10 ` Nicolin Chen
2025-02-28 1:31 ` [PATCH v2 3/4] iommu: Drop sw_msi from iommu_domain Nicolin Chen
2025-02-28 1:31 ` [PATCH v2 4/4] iommu: Turn iova_cookie to dma-iommu private pointer Nicolin Chen
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