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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Jose Abreu <joabreu@synopsys.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas RZ/V2H(P) SoC
Date: Sun, 2 Mar 2025 21:49:55 +0000	[thread overview]
Message-ID: <Z8TSgxLqNwZ6zc3V@shell.armlinux.org.uk> (raw)
In-Reply-To: <CA+V-a8tjOmn4BAamr6BrniTiyMxNYMCRrnZaqzEs_Xr=359Rvg@mail.gmail.com>

On Sun, Mar 02, 2025 at 09:43:47PM +0000, Lad, Prabhakar wrote:
> On Sun, Mar 2, 2025 at 9:39 PM Andrew Lunn <andrew@lunn.ch> wrote:
> > > > Your SoC designer really implemented the 0° and 180° as two separate
> > > > independently controllable clocks?
> > > >
> > > Yes there are separate bits to turn ON/OFF the 0° and 180° clocks.
> >
> > Do you know what the clock tree actually looks like? I can think of
> > two different ways this could be implemented:
> >
> > ----+----------on/off---
> >     |
> >     +----not---on/off---
> >
> > or
> >
> > -------on/off-+------------------
> >               |
> >               +---not---on/off---
> >
> > In the first, the clocks are siblings. In the second there is
> > parent/child relationship.
> >
> It's the first case in this SoC.

Umm, okay. I'll just pick my jaw up off the floor. :D

Given that, then yes, go with your existing clock binding, because
that's the most sensible.

However, what would be useful for future maintenance is to put some
commentry at the top of the new glue file describing this (pictorially)
so that when someone looks at this later we know why it is this way.
It'll be useful information if someone else does the same because then
we can say "hey, we already have a binding for this situation!"

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2025-03-02 21:50 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-02 18:18 [PATCH 0/3] Add GBETH glue layer driver for Renesas RZ/V2H(P) SoC Prabhakar
2025-03-02 18:18 ` [PATCH 1/3] dt-bindings: net: dwmac: Increase 'maxItems' for 'interrupts' and 'interrupt-names' Prabhakar
2025-03-03 15:26   ` Rob Herring
2025-03-03 15:58     ` Lad, Prabhakar
2025-03-03 16:34       ` Andrew Lunn
2025-03-03 20:40         ` Lad, Prabhakar
2025-03-02 18:18 ` [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas RZ/V2H(P) SoC Prabhakar
2025-03-02 19:10   ` Andrew Lunn
2025-03-02 19:28     ` Russell King (Oracle)
2025-03-02 21:33       ` Andrew Lunn
2025-03-03 15:15         ` Rob Herring
2025-03-02 19:25   ` Andrew Lunn
2025-03-02 20:41     ` Lad, Prabhakar
2025-03-02 21:01       ` Russell King (Oracle)
2025-03-02 21:22         ` Lad, Prabhakar
2025-03-02 21:39           ` Andrew Lunn
2025-03-02 21:43             ` Lad, Prabhakar
2025-03-02 21:49               ` Russell King (Oracle) [this message]
2025-03-02 21:51                 ` Russell King (Oracle)
2025-03-02 22:03                   ` Lad, Prabhakar
2025-03-02 18:18 ` [PATCH 3/3] net: stmmac: Add DWMAC glue layer for Renesas GBETH Prabhakar
2025-03-02 19:33   ` Russell King (Oracle)
2025-03-02 20:05     ` Russell King (Oracle)
2025-03-02 21:20     ` Lad, Prabhakar
2025-03-02 21:44       ` Russell King (Oracle)
2025-03-02 22:02         ` Lad, Prabhakar
2025-03-03 11:19           ` Russell King (Oracle)
2025-03-03 16:04             ` Lad, Prabhakar
2025-03-03 16:32               ` Russell King (Oracle)
2025-03-05 21:26                 ` Lad, Prabhakar
2025-03-06  0:31                   ` Russell King (Oracle)
2025-03-08 13:20                     ` Lad, Prabhakar
2025-03-04  6:58             ` Biju Das
2025-03-04 10:00               ` Russell King (Oracle)
2025-03-04 10:56                 ` Biju Das
2025-03-04 11:16                   ` Russell King (Oracle)
2025-03-04 14:04                 ` Geert Uytterhoeven
2025-03-03  9:41       ` Lad, Prabhakar
2025-03-03  9:58         ` Russell King (Oracle)
2025-03-03 10:58           ` Russell King (Oracle)
2025-03-03 10:40   ` Geert Uytterhoeven
2025-03-03 10:44     ` Lad, Prabhakar
2025-03-03 10:54     ` Russell King (Oracle)
2025-03-06 13:11   ` Geert Uytterhoeven
2025-03-08 12:44     ` Lad, Prabhakar

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