[PATCH v1 28/40] x86/cacheinfo: Use enums for cache descriptor types

Ahmed S. Darwish
2025-03-04T08:53:39Z

The leaf 0x2 one-byte cache descriptor types:

CACHE_L1_INST
CACHE_L1_DATA
CACHE_L2
CACHE_L3

are just discriminators to be used within the cache_table[] mapping.
Their specific values are irrelevant.

Use enums for such types.

Make the enum packed and static assert that its values remain within a
single byte so that the cache_table[] array size do not go out of hand.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
arch/x86/include/asm/cpuid/types.h | 14 ++++++++++++++
arch/x86/kernel/cpu/cacheinfo.c | 9 ++-------
2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 50f6046a57b9..0051d8c2b9ee 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -2,6 +2,8 @@
#ifndef _ASM_X86_CPUID_TYPES_H
#define _ASM_X86_CPUID_TYPES_H

+#include <linux/build_bug.h>
+#include <linux/compiler_attributes.h>
#include <linux/types.h>

#include <asm/cpuid.h>
@@ -76,4 +78,16 @@ static inline void get_leaf_0x2_regs(union leaf_0x2_regs *regs)
/* Skip the first byte as it is not a descriptor */ \
for (desc = &(regs).desc[1]; desc < &(regs).desc[16]; desc++)

+/*
+ * Leaf 0x2 1-byte descriptors' cache types
+ * To be used for their mappings at cache_table[]
+ */
+enum _cache_table_type {
+ CACHE_L1_INST,
+ CACHE_L1_DATA,
+ CACHE_L2,
+ CACHE_L3,
+} __packed;
+static_assert(sizeof(enum _cache_table_type) == 1);
+
#endif /* _ASM_X86_CPUID_TYPES_H */
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 9e87321466fe..a7fccbab268d 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -23,11 +23,6 @@

#include "cpu.h"

-#define CACHE_L1_INST 1
-#define CACHE_L1_DATA 2
-#define CACHE_L2 3
-#define CACHE_L3 4
-
/* Shared last level cache maps */
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);

@@ -41,7 +36,7 @@ unsigned int memory_caching_control __ro_after_init;

struct _cache_table {
unsigned char descriptor;
- char cache_type;
+ enum _cache_table_type type;
short size;
};

@@ -517,7 +512,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)
if (!entry)
continue;

- switch (entry->cache_type) {
+ switch (entry->type) {
case CACHE_L1_INST: l1i += entry->size; break;
case CACHE_L1_DATA: l1d += entry->size; break;
case CACHE_L2: l2 += entry->size; break;
--
2.48.1