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Thu, 06 Mar 2025 05:08:41 -0800 (PST) Received: from krava ([2a00:102a:401e:9b3a:b228:9e66:580a:3bc8]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e5c768c798sm930867a12.66.2025.03.06.05.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 05:08:40 -0800 (PST) From: Jiri Olsa X-Google-Original-From: Jiri Olsa Date: Thu, 6 Mar 2025 14:08:38 +0100 To: lirongqing Cc: olsajiri@gmail.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH][next] perf/x86/intel/bts: check if bts_ctx is allocated when call bts functions Message-ID: References: <20250306051102.2642-1-lirongqing@baidu.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250306051102.2642-1-lirongqing@baidu.com> On Thu, Mar 06, 2025 at 01:11:02PM +0800, lirongqing wrote: > From: Li RongQing > > bts_ctx maybe not allocated, for example if the cpu has X86_FEATURE_PTI, > but intel_bts_disable/enable_local and intel_bts_interrupt are called > unconditionally from intel_pmu_handle_irq and exploding on accessing > bts_ctx > > so check if bts_ctx is allocated when call bts functions > > Fixes: 3acfcefa795c "(perf/x86/intel/bts: Allocate bts_ctx only if necessary)" > Reported-by: Jiri Olsa Tested-by: Jiri Olsa thanks, jirka > Suggested-by: Adrian Hunter > Suggested-by: Dave Hansen > Signed-off-by: Li RongQing > --- > arch/x86/events/intel/bts.c | 25 ++++++++++++++++++++----- > 1 file changed, 20 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c > index 8e09319..e8b3e7b 100644 > --- a/arch/x86/events/intel/bts.c > +++ b/arch/x86/events/intel/bts.c > @@ -338,9 +338,14 @@ static void bts_event_stop(struct perf_event *event, int flags) > > void intel_bts_enable_local(void) > { > - struct bts_ctx *bts = this_cpu_ptr(bts_ctx); > - int state = READ_ONCE(bts->state); > + struct bts_ctx *bts; > + int state; > > + if (!bts_ctx) > + return; > + > + bts = this_cpu_ptr(bts_ctx); > + state = READ_ONCE(bts->state); > /* > * Here we transition from INACTIVE to ACTIVE; > * if we instead are STOPPED from the interrupt handler, > @@ -358,7 +363,12 @@ void intel_bts_enable_local(void) > > void intel_bts_disable_local(void) > { > - struct bts_ctx *bts = this_cpu_ptr(bts_ctx); > + struct bts_ctx *bts; > + > + if (!bts_ctx) > + return; > + > + bts = this_cpu_ptr(bts_ctx); > > /* > * Here we transition from ACTIVE to INACTIVE; > @@ -450,12 +460,17 @@ bts_buffer_reset(struct bts_buffer *buf, struct perf_output_handle *handle) > int intel_bts_interrupt(void) > { > struct debug_store *ds = this_cpu_ptr(&cpu_hw_events)->ds; > - struct bts_ctx *bts = this_cpu_ptr(bts_ctx); > - struct perf_event *event = bts->handle.event; > + struct bts_ctx *bts; > + struct perf_event *event; > struct bts_buffer *buf; > s64 old_head; > int err = -ENOSPC, handled = 0; > > + if (!bts_ctx) > + return 0; > + > + bts = this_cpu_ptr(bts_ctx); > + event = bts->handle.event; > /* > * The only surefire way of knowing if this NMI is ours is by checking > * the write ptr against the PMI threshold. > -- > 2.9.4 >