Re: [PATCH v2] counter: 104-quad-8: Fix race condition between FLAG and CNTR reads

[William Breathitt Gray <william.gray@linaro.org>]

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On Sun, Mar 12, 2023 at 05:23:47PM -0400, William Breathitt Gray wrote:
> The Counter (CNTR) register is 24 bits wide, but we can have an
> effective 25-bit count value by setting bit 24 to the XOR of the Borrow
> flag and Carry flag. The flags can be read from the FLAG register, but a
> race condition exists: the Borrow flag and Carry flag are instantaneous
> and could change by the time the count value is read from the CNTR
> register.
> 
> Since the race condition could result in an incorrect 25-bit count
> value, remove support for 25-bit count values from this driver;
> hard-coded maximum count values are replaced by a LS7267_CNTR_MAX define
> for consistency and clarity.
> 
> Fixes: 28e5d3bb0325 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8")
> Cc: stable@vger.kernel.org
> Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
> @@ -156,19 +155,9 @@ static int quad8_count_read(struct counter_device *counter,
>  {
>  	struct quad8 *const priv = counter_priv(counter);
>  	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
> -	unsigned int flags;
> -	unsigned int borrow;
> -	unsigned int carry;
>  	unsigned long irqflags;
>  	int i;
>  
> -	flags = ioread8(&chan->control);
> -	borrow = flags & QUAD8_FLAG_BT;
> -	carry = !!(flags & QUAD8_FLAG_CT);
> -
> -	/* Borrow XOR Carry effectively doubles count range */
> -	*val = (unsigned long)(borrow ^ carry) << 24;

The count value is used later on so it should be initialized here; I'll
submit a v3 along with some backports as well for the other stable
kernels.

William Breathitt Gray

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