From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Sai Prakash Ranjan <quic_saipraka@quicinc.com>,
Juerg Haefliger <juerg.haefliger@canonical.com>,
linux-arm-msm@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
stable@vger.kernel.org
Subject: Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
Date: Mon, 6 Mar 2023 15:16:15 +0100 [thread overview]
Message-ID: <ZAX1r1xXgnJ7fwIX@hovoldconsulting.com> (raw)
In-Reply-To: <ZAXxYPZ/zarxcsNF@linaro.org>
On Mon, Mar 06, 2023 at 03:57:52PM +0200, Abel Vesa wrote:
> On 23-03-06 14:01:20, Johan Hovold wrote:
> > On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> > > The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> > > LLCC config registers. Fix that by using the slice ID values taken from
> > > the latest LLCC SC table.
> >
> > This still doesn't really explain what the impact of this bug is (e.g.
> > for people doing backports), but I guess this will do.
> >
>
> Sent a v4 here:
> https://lore.kernel.org/all/20230306135527.509796-1-abel.vesa@linaro.org/
Looks good, thanks!
Johan
next prev parent reply other threads:[~2023-03-06 14:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-19 16:57 [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP Abel Vesa
2023-03-06 13:01 ` Johan Hovold
2023-03-06 13:57 ` Abel Vesa
2023-03-06 14:16 ` Johan Hovold [this message]
2023-03-07 4:20 ` Bjorn Andersson
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