From: "Jason A. Donenfeld" <Jason@zx2c4.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
regressions@leemhuis.info, regressions@lists.linux.dev
Subject: Re: [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Wed, 22 Mar 2023 13:01:25 +0100 [thread overview]
Message-ID: <ZBruFRwt3rUVngPu@zx2c4.com> (raw)
In-Reply-To: <20230128172856.3814-7-jszhang@kernel.org>
Hi,
On Sun, Jan 29, 2023 at 01:28:49AM +0800, Jisheng Zhang wrote:
> Switch has_fpu() from static branch to the new helper
> riscv_has_extension_likely().
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/include/asm/switch_to.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
> index 11463489fec6..60f8ca01d36e 100644
> --- a/arch/riscv/include/asm/switch_to.h
> +++ b/arch/riscv/include/asm/switch_to.h
> @@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
>
> static __always_inline bool has_fpu(void)
> {
> - return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
> + return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
> + riscv_has_extension_likely(RISCV_ISA_EXT_d);
This causes programs to crash on kernels that are compiled with
CONFIG_RISCV_ALTERNATIVE=n. Since CONFIG_RISCV_ALTERNATIVE isn't
selectable, this is a problem.
You can try this out for yourself using the WireGuard test suite:
ARCH=riscv64 make -C tools/testing/selftests/wireguard/qemu -j$(nproc)
And you'll see the crash:
[ 2.172093] init.sh[45]: unhandled signal 4 code 0x1 at 0x00ffffff945a2170 in libc.so[ffffff94562000+8c000]
[ 2.174306] CPU: 0 PID: 45 Comm: init.sh Not tainted 6.3.0-rc3+ #1
[ 2.174981] Hardware name: riscv-virtio,qemu (DT)
[ 2.175639] epc : 00ffffff945a2170 ra : 00aaaaaae7332820 sp : 00fffffffd3e6c00
[ 2.176287] gp : 00aaaaaae73aff40 tp : 00ffffff945f1a50 t0 : 0000000000000000
[ 2.176858] t1 : 00aaaaaae7331f9c t2 : 0000000000000002 s0 : 00fffffffd3e6de0
[ 2.177427] s1 : 0000000000000002 a0 : 00aaaaaae73b7380 a1 : 00fffffffd3e6dc8
[ 2.177990] a2 : 00fffffffd3e6de0 a3 : 0000000000000000 a4 : 0000000000000000
[ 2.178524] a5 : 0000000000000002 a6 : 000000000000008b a7 : 0000000000000010
[ 2.179081] s2 : 00aaaaaae73327f0 s3 : 00ffffff945ef990 s4 : 00ffffff945f1988
[ 2.179796] s5 : 00ffffff945f1b48 s6 : 0000000000000000 s7 : 00000000000000e0
[ 2.180366] s8 : 00ffffff945f1d58 s9 : 00ffffff945ecb88 s10: 00ffffff945f17e0
[ 2.185464] s11: 0000000000000001 t3 : 00ffffff945a213c t4 : 0000000300000000
[ 2.186106] t5 : 0000000000000003 t6 : ffffffffffffffff
[ 2.186520] status: 0000000200000020 badaddr: 000000000000b920 cause: 0000000000000002
I bisected it to this commit:
702e64550b12 ("riscv: fpu: switch has_fpu() to riscv_has_extension_likely()")
Thanks,
Jason
next prev parent reply other threads:[~2023-03-22 12:01 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-28 17:28 [PATCH v5 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 01/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 02/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 03/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 05/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2023-03-22 12:01 ` Jason A. Donenfeld [this message]
2023-03-22 12:09 ` [PATCH] riscv: require alternatives framework when selecting FPU support Jason A. Donenfeld
2023-03-22 12:46 ` Andrew Jones
2023-03-22 15:17 ` Conor Dooley
2023-03-22 19:26 ` Andrew Jones
2023-03-22 19:44 ` Conor Dooley
2023-03-22 20:05 ` Conor Dooley
2023-03-22 20:19 ` Jason A. Donenfeld
2023-03-23 14:49 ` Conor Dooley
2023-03-23 15:56 ` Jason A. Donenfeld
2023-03-23 22:19 ` Conor Dooley
2023-01-28 17:28 ` [PATCH v5 07/13] riscv: module: move find_section to module.h Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 09/13] riscv: switch to relative alternative entries Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang
2023-01-28 17:28 ` [PATCH v5 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2023-02-02 23:39 ` [PATCH v5 00/13] riscv: improve boot time isa extensions handling Palmer Dabbelt
2023-02-02 23:40 ` patchwork-bot+linux-riscv
2023-02-12 15:43 ` Guenter Roeck
2023-02-12 15:59 ` Conor Dooley
2023-02-12 16:33 ` Conor Dooley
2023-02-12 17:06 ` Conor Dooley
2023-02-12 18:06 ` Conor Dooley
2023-02-12 18:14 ` Guenter Roeck
2023-02-12 18:20 ` Conor Dooley
2023-02-12 18:38 ` Guenter Roeck
2023-02-12 18:45 ` Conor Dooley
2023-02-12 20:27 ` Guenter Roeck
2023-02-12 20:39 ` Conor Dooley
2023-02-12 22:21 ` Guenter Roeck
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