From: William Breathitt Gray <william.gray@linaro.org>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Johannes Berg <johannes.berg@intel.com>,
linux-iio@vger.kernel.org, Jonathan Cameron <jic23@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/3] counter: 104-quad-8: Refactor to buffer states for CMR, IOR, and IDR
Date: Fri, 31 Mar 2023 14:24:28 -0400 [thread overview]
Message-ID: <ZCclXMQ2NIUOdjas@fedora> (raw)
In-Reply-To: <ZCFn+A6oAVNOe3yp@smile.fi.intel.com>
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On Mon, Mar 27, 2023 at 12:55:04PM +0300, Andy Shevchenko wrote:
> +Cc clang (for the ideas you might have, while the issue seems related to GCC[?] )
>
> On Sun, Mar 26, 2023 at 08:01:23PM -0400, William Breathitt Gray wrote:
> > On Fri, Mar 24, 2023 at 11:35:02AM -0400, William Breathitt Gray wrote:
> > > There are eight calls to quad8_control_register_update() in 104-quad-8:
> > >
> > > quad8_control_register_update(priv, priv->idr, id, DISABLE_INDEX_MODE, INDEX_MODE);
> > > quad8_control_register_update(priv, priv->cmr, id, mode_cfg, QUADRATURE_MODE);
> > > quad8_control_register_update(priv, priv->ior, event_node->channel, flg_pins, FLG_PINS);
> > > quad8_control_register_update(priv, priv->idr, channel_id, index_polarity, INDEX_POLARITY);
> > > quad8_control_register_update(priv, priv->idr, channel_id, synchronous_mode, INDEX_MODE);
> > > quad8_control_register_update(priv, priv->cmr, count->id, count_mode, COUNT_MODE);
> > > quad8_control_register_update(priv, priv->ior, count->id, enable, AB_GATE);
> > > quad8_control_register_update(priv, priv->ior, count->id, !preset_enable, LOAD_PIN);
> >
> > I attempted the cross-compiling using an x86-64 system and I was able to
> > recreate the build error. I tried to isolate the problem line by
> > commenting out quad8_control_register_update() calls and discover that
> > this appears to be an inline issue after all: if there are more than six
> > calls to quad8_control_register_update() are in the code, then the
> > '__bad_mask' build error occurs.
> >
> > The build error doesn't occur if I force the inline via __always_inline,
> > so I'll add that to quad8_control_register_update() to resolve this
> > issue and submit a v3 patchset later this week.
>
> Doe it mean it's a compiler error? Or is it a code error?
>
> I'm wondering if clang also fails here.
>
> --
> With Best Regards,
> Andy Shevchenko
Al, I think you were the one who introduced the field_multiplier()
implementation in commit 00b0c9b82663ac ("Add primitives for
manipulating bitfields both in host- and fixed-endian."). Is this build
error [0] expected in your opinion?
I see that the field specification must be a constant according to the
commit description, so does that mean a "const u8 field" parameter is
valid? Does the field_multiplier() implementation have an expectation
that the condition check will be evaluated by the compiler during the
build and bypass the __bad_mask() compile time error so that it doesn't
appear?
William Breathitt Gray
[0] https://lore.kernel.org/all/202303241128.WBKc4LIy-lkp@intel.com/
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next prev parent reply other threads:[~2023-03-31 20:43 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 21:25 [PATCH v2 0/3] Refactor 104-quad-8 to match device operations William Breathitt Gray
2023-03-23 21:25 ` [PATCH v2 1/3] counter: 104-quad-8: Utilize bitfield access macros William Breathitt Gray
2023-03-23 21:25 ` [PATCH v2 2/3] counter: 104-quad-8: Refactor to buffer states for CMR, IOR, and IDR William Breathitt Gray
2023-03-24 11:48 ` Andy Shevchenko
2023-03-24 11:50 ` Andy Shevchenko
2023-03-24 13:26 ` William Breathitt Gray
2023-03-24 13:48 ` Andy Shevchenko
2023-03-24 15:35 ` William Breathitt Gray
2023-03-27 0:01 ` William Breathitt Gray
2023-03-27 9:55 ` Andy Shevchenko
2023-03-31 18:24 ` William Breathitt Gray [this message]
2023-03-23 21:25 ` [PATCH v2 3/3] counter: 104-quad-8: Utilize helper functions to handle PR, FLAG and PSC William Breathitt Gray
2023-03-24 3:46 ` kernel test robot
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