From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 312CAC77B75 for ; Tue, 18 Apr 2023 07:39:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230420AbjDRHi7 (ORCPT ); Tue, 18 Apr 2023 03:38:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229681AbjDRHi4 (ORCPT ); Tue, 18 Apr 2023 03:38:56 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34FA73C1F; Tue, 18 Apr 2023 00:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681803535; x=1713339535; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Gvo+MqctEL5HSwatCbCQmqOpF34r5sqpuLtBI4pvBpM=; b=PrHtmRgBycnx2IPFtzyk4DICop9Hb7AmDhBebiv813P04MjmRLoYfNc7 gKHa+7lJvwYpwYVV4t7ZGh2bBloTLYJED8XhCxViQwqs/Bs14K1XOSGkI bWw3qAtz4gL7O9/JPhCRjMc+z1qNrrU/LWYyLTaWOCcO4r1VdKRbh/3hs il0aN73N5UL9FPde2kvEhMhlpntwqGp0Y9sXFn7+kTsFz+nJ6H+3ZO70/ i1TSAltam/3Gpwo0hFqAerwDb8XtSjYTN5+Roq9+bJzJrkSuVMZ1uv7Ww 3UEk6gR5ZjZFFTpXETTCDaGPw8nG4YCfeCC7ni1xGJAxK6BS80kRwJkDO A==; X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="345099113" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="345099113" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2023 00:38:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="690984273" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="690984273" Received: from smile.fi.intel.com ([10.237.72.54]) by orsmga002.jf.intel.com with ESMTP; 18 Apr 2023 00:38:52 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1pofvP-001VdU-1K; Tue, 18 Apr 2023 10:38:51 +0300 Date: Tue, 18 Apr 2023 10:38:51 +0300 From: Andy Shevchenko To: Joy Chakraborty Cc: Serge Semin , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, manugautam@google.com, rohitner@google.com Subject: Re: [PATCH v7 4/5] spi: dw: Add DMA address widths capability check Message-ID: References: <20230418052902.1336866-1-joychakr@google.com> <20230418052902.1336866-5-joychakr@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230418052902.1336866-5-joychakr@google.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote: > Store address width capabilities of DMA controller during init and check > the same per transfer to make sure the bits/word requirement can be met. > > Current DW DMA driver requires both tx and rx channel to be configured > and functional hence a subset of both tx and rx channel address width > capability is checked with the width requirement(n_bytes) for a > transfer. ... > + /* > + * Assuming both channels belong to the same DMA controller hence the > + * address width capabilities most likely would be the same. > + */ I had a small comment on this In v6 thread. -- With Best Regards, Andy Shevchenko