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Sun, 09 Apr 2023 07:09:44 -0700 (PDT) Received: from linaro.org ([188.25.26.161]) by smtp.gmail.com with ESMTPSA id dx5-20020a170906a84500b0094a6cf3b642sm640241ejb.142.2023.04.09.07.09.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Apr 2023 07:09:43 -0700 (PDT) Date: Sun, 9 Apr 2023 17:09:42 +0300 From: Abel Vesa To: "Peng Fan (OSS)" Cc: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jacky Bai , Peng Fan Subject: Re: [PATCH 2/5] clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate Message-ID: References: <20230331063814.2462059-1-peng.fan@oss.nxp.com> <20230331063814.2462059-3-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230331063814.2462059-3-peng.fan@oss.nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23-03-31 14:38:11, Peng Fan (OSS) wrote: > From: Jacky Bai > > If a divider's parent clock has fractional part, it will hard to round out a > more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags > for such divider to get a more accurate clock rate. > > Reviewed-by: Peng Fan > Signed-off-by: Jacky Bai > Signed-off-by: Peng Fan Reviewed-by: Abel Vesa > --- > drivers/clk/imx/clk-imx8ulp.c | 16 ++++++++-------- > drivers/clk/imx/clk.h | 9 +++++++++ > 2 files changed, 17 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c > index 89121037a8f0..3cf4b094dfff 100644 > --- a/drivers/clk/imx/clk-imx8ulp.c > +++ b/drivers/clk/imx/clk-imx8ulp.c > @@ -275,14 +275,14 @@ static int imx8ulp_clk_cgc2_init(struct platform_device *pdev) > clks[IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE] = imx_clk_hw_gate_dis("pll4_pfd2_div2_gate", "pll4_pfd2", base + 0x60c, 15); > clks[IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE] = imx_clk_hw_gate_dis("pll4_pfd3_div1_gate", "pll4_pfd3", base + 0x60c, 23); > clks[IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE] = imx_clk_hw_gate_dis("pll4_pfd3_div2_gate", "pll4_pfd3", base + 0x60c, 31); > - clks[IMX8ULP_CLK_PLL4_PFD0_DIV1] = imx_clk_hw_divider("pll4_pfd0_div1", "pll4_pfd0_div1_gate", base + 0x608, 0, 6); > - clks[IMX8ULP_CLK_PLL4_PFD0_DIV2] = imx_clk_hw_divider("pll4_pfd0_div2", "pll4_pfd0_div2_gate", base + 0x608, 8, 6); > - clks[IMX8ULP_CLK_PLL4_PFD1_DIV1] = imx_clk_hw_divider("pll4_pfd1_div1", "pll4_pfd1_div1_gate", base + 0x608, 16, 6); > - clks[IMX8ULP_CLK_PLL4_PFD1_DIV2] = imx_clk_hw_divider("pll4_pfd1_div2", "pll4_pfd1_div2_gate", base + 0x608, 24, 6); > - clks[IMX8ULP_CLK_PLL4_PFD2_DIV1] = imx_clk_hw_divider("pll4_pfd2_div1", "pll4_pfd2_div1_gate", base + 0x60c, 0, 6); > - clks[IMX8ULP_CLK_PLL4_PFD2_DIV2] = imx_clk_hw_divider("pll4_pfd2_div2", "pll4_pfd2_div2_gate", base + 0x60c, 8, 6); > - clks[IMX8ULP_CLK_PLL4_PFD3_DIV1] = imx_clk_hw_divider("pll4_pfd3_div1", "pll4_pfd3_div1_gate", base + 0x60c, 16, 6); > - clks[IMX8ULP_CLK_PLL4_PFD3_DIV2] = imx_clk_hw_divider("pll4_pfd3_div2", "pll4_pfd3_div2_gate", base + 0x60c, 24, 6); > + clks[IMX8ULP_CLK_PLL4_PFD0_DIV1] = imx_clk_hw_divider_closest("pll4_pfd0_div1", "pll4_pfd0_div1_gate", base + 0x608, 0, 6); > + clks[IMX8ULP_CLK_PLL4_PFD0_DIV2] = imx_clk_hw_divider_closest("pll4_pfd0_div2", "pll4_pfd0_div2_gate", base + 0x608, 8, 6); > + clks[IMX8ULP_CLK_PLL4_PFD1_DIV1] = imx_clk_hw_divider_closest("pll4_pfd1_div1", "pll4_pfd1_div1_gate", base + 0x608, 16, 6); > + clks[IMX8ULP_CLK_PLL4_PFD1_DIV2] = imx_clk_hw_divider_closest("pll4_pfd1_div2", "pll4_pfd1_div2_gate", base + 0x608, 24, 6); > + clks[IMX8ULP_CLK_PLL4_PFD2_DIV1] = imx_clk_hw_divider_closest("pll4_pfd2_div1", "pll4_pfd2_div1_gate", base + 0x60c, 0, 6); > + clks[IMX8ULP_CLK_PLL4_PFD2_DIV2] = imx_clk_hw_divider_closest("pll4_pfd2_div2", "pll4_pfd2_div2_gate", base + 0x60c, 8, 6); > + clks[IMX8ULP_CLK_PLL4_PFD3_DIV1] = imx_clk_hw_divider_closest("pll4_pfd3_div1", "pll4_pfd3_div1_gate", base + 0x60c, 16, 6); > + clks[IMX8ULP_CLK_PLL4_PFD3_DIV2] = imx_clk_hw_divider_closest("pll4_pfd3_div2", "pll4_pfd3_div2_gate", base + 0x60c, 24, 6); > > clks[IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div1_gate", "sosc", base + 0x108, 7); > clks[IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div2_gate", "sosc", base + 0x108, 15); > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index bb105d6e5b39..ca1f75eb3197 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -356,6 +356,15 @@ static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, > CLK_SET_RATE_PARENT, mult, div); > } > > +static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name, > + const char *parent, > + void __iomem *reg, u8 shift, > + u8 width) > +{ > + return clk_hw_register_divider(NULL, name, parent, 0, > + reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock); > +} > + > static inline struct clk_hw *__imx_clk_hw_divider(const char *name, > const char *parent, > void __iomem *reg, u8 shift, > -- > 2.37.1 >