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Date:   Wed, 12 Apr 2023 22:06:33 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Swapnil Jakhade <sjakhade@cadence.com>
Cc:     kishon@kernel.org, linux-phy@lists.infradead.org,
        linux-kernel@vger.kernel.org, mparab@cadence.com,
        rogerq@kernel.org, s-vadapalli@ti.com
Subject: Re: [PATCH v2] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
 configuration
Message-ID: <ZDbeEUKIZ7kJPm3k@matsya>
References: <20230403085644.10187-1-sjakhade@cadence.com>
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On 03-04-23, 10:56, Swapnil Jakhade wrote:
> Add register sequences for PCIe + SGMII PHY multilink configuration.
> This has been validated on TI J7 platforms.

Applied, thanks

-- 
~Vinod