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From: Daniel Golle <daniel@makrotopia.org>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@collabora.com>
Subject: Re: [PATCH net-next 0/8] Improvements for RealTek 2.5G Ethernet PHYs
Date: Thu, 11 May 2023 19:14:48 +0200	[thread overview]
Message-ID: <ZF0iiDIZQzR8vMvm@pidgin.makrotopia.org> (raw)
In-Reply-To: <55c11fd9-54cf-4460-a10c-52ff62b46a4c@lunn.ch>

On Thu, May 11, 2023 at 02:28:15AM +0200, Andrew Lunn wrote:
> On Thu, May 11, 2023 at 12:53:22AM +0200, Daniel Golle wrote:
> > Improve support for RealTek 2.5G Ethernet PHYs (RTL822x series).
> > The PHYs can operate with Clause-22 and Clause-45 MDIO.
> > 
> > When using Clause-45 it is desireable to avoid rate-adapter mode and
> > rather have the MAC interface mode follow the PHY speed. The PHYs
> > support 2500Base-X for 2500M, and Cisco SGMII for 1000M/100M/10M.
> 
> I don't see what clause-45 has to do with this. The driver knows that
> both C22 and C45 addresses spaces exists in the hardware. It can do
> reads/writes on both. If the bus master does not support C45, C45 over
> C22 will be performed by the core.

My understanding is/was that switching the SerDes interface mode is only
intended with Clause-45 PHYs, derived from this comment and code:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/phylink.c#n1661


Hence I concluded that for Clause-22 PHYs we expect the interface mode
to always remain the same, while many Clause-45 PHYs require switching
the SerDes interface mode depending on the speed of the external link.
Trying to use interface mode switching (in the .read_status function)
with is_c45 == false also just didn't work well:

https://github.com/openwrt/openwrt/pull/11990#issuecomment-1503160296


Up to 1000M this has no really been a problem, as the Cisco SGMII SerDes
supports 10M, 100M and 1000M speeds. Starting with 2500M things have
became more complicated, and we usually have the choice of either have
the MAC<->PHY link operate at a contant mode and speed (e.g. 2500Base-X)
or having to switch the MAC<->PHY interface mode (e.g. between
2500Base-X and SGMII) depending on whether the link speed on the
external interface is 2500M or not.

Looking at PHYs which support speeds beyond one gigabit/sec due to the
higher complexity and need for a larger register space most of them are
managed using Clause-45 MDIO. 2500Base-T PHYs are kind of the exception
because some of them (esp. RealTek) are still mostly being managed using
Clause-22 MDIO using proprietary paging mechanisms to enlarge the
register space.

I also don't like overloading the meaning of is_c45 to decide whether
rate-adapter mode should be used or not, neither do I like the idea to
tie the use of phylink to using SGMII in-band-status or not -- but at
this point both do correlate and there aren't any other feature flags or
validation methods to do it in a better way. In the end this can also
just be solved by documenation, ie. makeing sure that those facts are
well understood: interface mode switching only being supported when
using Clause-45 MDIO and also the fact that phylink expects operating
Cisco SGMII without in-band-status when connecting to a managed PHY.


  reply	other threads:[~2023-05-11 17:16 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-10 22:53 [PATCH net-next 0/8] Improvements for RealTek 2.5G Ethernet PHYs Daniel Golle
2023-05-10 22:53 ` [PATCH net-next 1/8] net: phy: realtek: rtl8221: allow to configure SERDES mode Alexander Couzens
2023-05-10 22:56   ` [PATCH " Daniel Golle
2023-05-11  0:34   ` Andrew Lunn
2023-05-11  0:38   ` Andrew Lunn
2023-05-11 11:50     ` Daniel Golle
2023-05-11  0:41   ` Andrew Lunn
2023-05-11 11:53     ` Daniel Golle
2023-05-11  7:53   ` [PATCH net-next " Steen Hegelund
2023-05-10 22:54 ` [PATCH net-next 2/8] net: phy: realtek: switch interface mode for RTL822x series Chukun Pan
2023-05-10 22:57   ` Daniel Golle
2023-05-10 22:55 ` [PATCH net-next 3/8] net: phy: realtek: use genphy_soft_reset for 2.5G PHYs Daniel Golle
2023-05-10 22:57   ` Daniel Golle
2023-05-10 22:58 ` [PATCH net-next 4/8] net: phy: realtek: disable SGMII in-band AN " Daniel Golle
2023-05-10 22:58 ` [PATCH net-next 5/8] net: phy: realtek: make sure paged read is protected by mutex Daniel Golle
2023-05-10 22:59 ` [PATCH net-next 6/8] net: phy: realtek: use inline functions for 10GbE advertisement Daniel Golle
2023-05-10 22:59 ` [PATCH net-next 7/8] net: phy: realtek: check validity of 10GbE link-partner advertisement Daniel Golle
2023-05-10 23:00 ` [PATCH net-next 8/8] net: phy: realtek: setup ALDPS on RTL8221B Daniel Golle
2023-05-11  0:28 ` [PATCH net-next 0/8] Improvements for RealTek 2.5G Ethernet PHYs Andrew Lunn
2023-05-11 17:14   ` Daniel Golle [this message]
2023-05-11 17:30     ` Russell King (Oracle)
2023-05-11 18:09       ` Russell King (Oracle)
2023-05-13 17:52         ` Daniel Golle
2023-05-13 19:24           ` Russell King (Oracle)
2023-05-11  5:29 ` Heiner Kallweit
2023-05-11 11:44   ` Daniel Golle

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