From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A459AC19F20 for ; Tue, 2 May 2023 20:43:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229984AbjEBUnS (ORCPT ); Tue, 2 May 2023 16:43:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229700AbjEBUnQ (ORCPT ); Tue, 2 May 2023 16:43:16 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C75310D9 for ; Tue, 2 May 2023 13:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683060193; x=1714596193; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=iL8g1yXa/B6Zqtk9KfJ6MRfSv7ALi5Zfa0rUJdGY2kc=; b=M+AOUQ/ebaW4Xe9nN3KM+Xlm3vTnQt2LqNOaTQgIXv/1YwHODFwKctBw 7YR4tPYTfajk3q+STDxlSVxSzWcbyOizId3QLg7YQpoAd90ud4/K1hEf4 D2sr5LQ5sfwGOfKQEL1RwS/Ca5V5h9yzb7lFtNr6QAs7WGmxf+L3qVUAk fD3ClRP182AXlKZRUzrEd3egBuFQXTWdYRvkPwGCkvhCc+sDYqydR6hjN XiZvtNIkjkbMo3Zq9e6/fZ0IN7xMAZo+stUHyDEqLUt9GZLbBaRWkdAj0 jFuR+6LlNMznxMLiXOpFQV5zyDHzTOyy/tyB212IuwdaO0b0i1/vatotj Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10698"; a="413952732" X-IronPort-AV: E=Sophos;i="5.99,245,1677571200"; d="scan'208";a="413952732" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2023 13:43:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10698"; a="840435241" X-IronPort-AV: E=Sophos;i="5.99,245,1677571200"; d="scan'208";a="840435241" Received: from pliberma-mobl.ger.corp.intel.com (HELO intel.com) ([10.252.61.88]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2023 13:43:07 -0700 Date: Tue, 2 May 2023 22:42:52 +0200 From: Andi Shyti To: Janusz Krzysztofik Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , David Hildenbrand , Yu Zhao , Juergen Gross , linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Andrzej Hajda , Nirmoy Das , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [RFC PATCH] x86/mm: Fix PAT bit missing from page protection modify mask Message-ID: References: <20230424123524.17008-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230424123524.17008-1-janusz.krzysztofik@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, a kind reminder on this patch, would be fantastic if anyone from the x86 maintainers cha give it a look. The patch has been tested thoroughly and even if it's marked as an RFC in my opinion it can be already considered for a proper review. Thanks, Andi On Mon, Apr 24, 2023 at 02:35:24PM +0200, Janusz Krzysztofik wrote: > Visible glitches have been observed when running graphics applications on > Linux under Xen hypervisor. Those observations have been confirmed with > failures from kms_pwrite_crc Intel GPU test that verifies data coherency > of DRM frame buffer objects using hardware CRC checksums calculated by > display controllers, exposed to userspace via debugfs. Affected > processing paths have then been identified with new test variants that > mmap the objects using different methods and caching modes. > > When running as a Xen PV guest, Linux uses Xen provided PAT configuration > which is different from its native one. In particular, Xen specific PTE > encoding of write-combining caching, likely used by graphics applications, > differs from the Linux default one found among statically defined minimal > set of supported modes. Since Xen defines PTE encoding of the WC mode as > _PAGE_PAT, it no longer belongs to the minimal set, depends on correct > handling of _PAGE_PAT bit, and can be mismatched with write-back caching. > > When a user calls mmap() for a DRM buffer object, DRM device specific > .mmap file operation, called from mmap_region(), takes care of setting PTE > encoding bits in a vm_page_prot field of an associated virtual memory area > structure. Unfortunately, _PAGE_PAT bit is not preserved when the vma's > .vm_flags are then applied to .vm_page_prot via vm_set_page_prot(). Bits > to be preserved are determined with _PAGE_CHG_MASK symbol that doesn't > cover _PAGE_PAT. As a consequence, WB caching is requested instead of WC > when running under Xen (also, WP is silently changed to WT, and UC > downgraded to UC_MINUS). When running on bare metal, WC is not affected, > but WP and WT extra modes are unintentionally replaced with WC and UC, > respectively. > > WP and WT modes, encoded with _PAGE_PAT bit set, were introduced by commit > 281d4078bec3 ("x86: Make page cache mode a real type"). Care was taken > to extend _PAGE_CACHE_MASK symbol with that additional bit, but that > symbol has never been used for identification of bits preserved when > applying page protection flags. Support for all cache modes under Xen, > including the problematic WC mode, was then introduced by commit > 47591df50512 ("xen: Support Xen pv-domains using PAT"). > > Extend bitmask used by pgprot_modify() for selecting bits to be preserved > with _PAGE_PAT bit. However, since that bit can be reused as _PAGE_PSE, > and the _PAGE_CHG_MASK symbol, primarly used by pte_modify(), is likely > intentionally defined with that bit not set, keep that symbol unchanged. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7648 > Fixes: 281d4078bec3 ("x86: Make page cache mode a real type") > Signed-off-by: Janusz Krzysztofik > Cc: stable@vger.kernel.org # v3.19+ > --- > arch/x86/include/asm/pgtable.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h > index 7425f32e52932..f797f8da2e5b6 100644 > --- a/arch/x86/include/asm/pgtable.h > +++ b/arch/x86/include/asm/pgtable.h > @@ -654,8 +654,10 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) > #define pgprot_modify pgprot_modify > static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) > { > - pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; > - pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; > + unsigned long mask = _PAGE_CHG_MASK | _PAGE_CACHE_MASK; > + > + pgprotval_t preservebits = pgprot_val(oldprot) & mask; > + pgprotval_t addbits = pgprot_val(newprot) & ~mask; > return __pgprot(preservebits | addbits); > } > > -- > 2.40.0