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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id p6-20020a815b06000000b00545a081847fsm8933405ywb.15.2023.05.03.14.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 14:08:24 -0700 (PDT) Date: Wed, 3 May 2023 17:08:22 -0400 From: Brian Masney To: Andrew Halaney Cc: linux-kernel@vger.kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 0/2] Add EMAC3 support for sa8540p-ride (devicetree bits) Message-ID: References: <20230501205105.2518373-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230501205105.2518373-1-ahalaney@redhat.com> User-Agent: Mutt/2.2.9 (2022-11-12) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 01, 2023 at 03:51:03PM -0500, Andrew Halaney wrote: > This is a forward port / upstream refactor of code delivered > downstream by Qualcomm over at [0] to enable the DWMAC5 based > implementation called EMAC3 on the sa8540p-ride dev board. > > >From what I can tell with the board schematic in hand, > as well as the code delivered, the main changes needed are: > > 1. A new address space layout for dwmac5/EMAC3 MTL/DMA regs > 2. A new programming sequence required for the EMAC3 base platforms > > This series addresses the devicetree changes to support this > hardware bringup. > > As requested[1], it has been split up by compile deps / maintainer tree. > The associated v4 of the netdev specific changes can be found at [2], > and is merged. > > The clock patch from this series was picked up from v5, leaving just the > devicetree bits here. > > Together, they result in the ethernet controller working for > both controllers on this platform. Reviewed-by: Brian Masney