* [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option
@ 2023-05-10 20:44 Yangtao Li
2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Yangtao Li @ 2023-05-10 20:44 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Jisheng Zhang, Icenowy Zheng, Wei Fu, Yangtao Li, linux-riscv,
linux-kernel
From: Jisheng Zhang <jszhang@kernel.org>
The first SoC in the T-HEAD series is light(a.k.a th1520), containing
quad T-HEAD C910 cores.
Cc: Icenowy Zheng <uwu@icenowy.me>
Cc: Wei Fu <wefu@redhat.com>
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Yangtao Li <frank.li@vivo.com>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..ce10a38dff37 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -41,6 +41,12 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_THEAD
+ bool "T-HEAD RISC-V SoCs"
+ select ERRATA_THEAD
+ help
+ This enables support for the RISC-V based T-HEAD SoCs.
+
config ARCH_VIRT
def_bool SOC_VIRT
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li @ 2023-05-10 20:44 ` Yangtao Li 2023-05-11 0:35 ` Yixun Lan ` (2 more replies) 2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li ` (3 subsequent siblings) 4 siblings, 3 replies; 14+ messages in thread From: Yangtao Li @ 2023-05-10 20:44 UTC (permalink / raw) To: Jisheng Zhang, Wei Fu, Yangtao Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: Icenowy Zheng, linux-riscv, devicetree, linux-kernel From: Jisheng Zhang <jszhang@kernel.org> Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Cc: Icenowy Zheng <uwu@icenowy.me> Cc: Wei Fu <wefu@redhat.com> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Yangtao Li <frank.li@vivo.com> --- v2: -remove reset-sample -convert to use thead,c900-plic -add pvt node -add thermal-zones arch/riscv/boot/dts/thead/th1520.dtsi | 491 ++++++++++++++++++++++++++ 1 file changed, 491 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi new file mode 100644 index 000000000000..d1d94098b6bf --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "thead,th1520"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&c910_0>; + }; + + core1 { + cpu = <&c910_1>; + }; + + core2 { + cpu = <&c910_2>; + }; + + core3 { + cpu = <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + pvt_clk: pvt-clock { + compatible = "fixed-clock"; + clock-frequency = <73728000>; + clock-output-names = "pvt_clk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,c900-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,ndev = <240>; + + }; + + clint: timer@ffdc000000 { + compatible = "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x4000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb_clk>, <&apb_clk>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + pvt: pvt@fffff4e000 { + compatible = "moortec,mr75203"; + reg = <0xff 0xfff4e000 0x0 0x80>, + <0xff 0xfff4e080 0x0 0x100>, + <0xff 0xfff4e180 0x0 0x680>, + <0xff 0xfff4e800 0x0 0x600>; + reg-names = "common", "ts", "pd", "vm"; + clocks = <&pvt_clk>; + /* TODO: add reset */ + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&pvt 0>; + + trips { + trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li @ 2023-05-11 0:35 ` Yixun Lan 2023-05-11 0:39 ` Jisheng Zhang 2023-05-11 9:05 ` Krzysztof Kozlowski 2 siblings, 0 replies; 14+ messages in thread From: Yixun Lan @ 2023-05-11 0:35 UTC (permalink / raw) To: Yangtao Li Cc: Jisheng Zhang, Wei Fu, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Icenowy Zheng, linux-riscv, devicetree, linux-kernel Hi Yangtao: On 04:44 Thu 11 May , Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Add initial device tree for the TH1520 RISC-V SoC by > T-HEAD. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -remove reset-sample > -convert to use thead,c900-plic > -add pvt node > -add thermal-zones > arch/riscv/boot/dts/thead/th1520.dtsi | 491 ++++++++++++++++++++++++++ > 1 file changed, 491 insertions(+) > create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > new file mode 100644 > index 000000000000..d1d94098b6bf > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -0,0 +1,491 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Alibaba Group Holding Limited. > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "thead,th1520"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <3000000>; > + > + c910_0: cpu@0 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <0>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_1: cpu@1 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <1>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_2: cpu@2 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <2>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_3: cpu@3 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <3>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&c910_0>; > + }; > + > + core1 { > + cpu = <&c910_1>; > + }; > + > + core2 { > + cpu = <&c910_2>; > + }; > + > + core3 { > + cpu = <&c910_3>; > + }; > + }; > + }; > + > + l2_cache: l2-cache { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-size = <1048576>; > + cache-sets = <1024>; > + cache-unified; > + }; > + }; > + > + osc: oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_24m"; > + #clock-cells = <0>; > + }; > + > + osc_32k: 32k-oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_32k"; > + #clock-cells = <0>; > + }; > + > + apb_clk: apb-clk-clock { is this a real "fixed-clock" according to hardware spec, or written intentional? e.g before common clk is implemented.. I'd suggest at least document the dummy/fake fixed clocks, so people will know things need to do in the future? > + compatible = "fixed-clock"; > + clock-output-names = "apb_clk"; > + #clock-cells = <0>; > + }; > + > + uart_sclk: uart-sclk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "uart_sclk"; > + #clock-cells = <0>; > + }; > + > + pvt_clk: pvt-clock { > + compatible = "fixed-clock"; > + clock-frequency = <73728000>; > + clock-output-names = "pvt_clk"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + plic: interrupt-controller@ffd8000000 { > + compatible = "thead,c900-plic"; > + reg = <0xff 0xd8000000 0x0 0x01000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>; > + interrupt-controller; > + #interrupt-cells = <2>; > + riscv,ndev = <240>; > + > + }; > + > + clint: timer@ffdc000000 { > + compatible = "thead,c900-clint"; > + reg = <0xff 0xdc000000 0x0 0x00010000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>; > + }; > + > + uart0: serial@ffe7014000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7014000 0x0 0x4000>; > + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: serial@ffe7f00000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f00000 0x0 0x4000>; > + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@ffe7f04000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f04000 0x0 0x4000>; > + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + gpio2: gpio@ffe7f34000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f34000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portc: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio3: gpio@ffe7f38000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f38000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portd: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio0: gpio@ffec005000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec005000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porta: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio1: gpio@ffec006000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec006000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + uart2: serial@ffec010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xec010000 0x0 0x4000>; > + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + dmac0: dma-controller@ffefc00000 { > + compatible = "snps,axi-dma-1.01a"; > + reg = <0xff 0xefc00000 0x0 0x1000>; > + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&apb_clk>, <&apb_clk>; > + clock-names = "core-clk", "cfgr-clk"; > + #dma-cells = <1>; > + dma-channels = <4>; > + snps,block-size = <65536 65536 65536 65536>; > + snps,priority = <0 1 2 3>; > + snps,dma-masters = <1>; > + snps,data-width = <4>; > + snps,axi-max-burst-len = <16>; > + status = "disabled"; > + }; > + > + timer0: timer@ffefc32000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer1: timer@ffefc32014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer2: timer@ffefc32028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer3: timer@ffefc3203c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc3203c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + uart4: serial@fff7f08000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f08000 0x0 0x4000>; > + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart5: serial@fff7f0c000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f0c000 0x0 0x4000>; > + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + timer4: timer@ffffc33000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer5: timer@ffffc33014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer6: timer@ffffc33028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer7: timer@ffffc3303c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc3303c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + ao_gpio0: gpio@fffff41000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff41000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porte: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + pvt: pvt@fffff4e000 { > + compatible = "moortec,mr75203"; > + reg = <0xff 0xfff4e000 0x0 0x80>, > + <0xff 0xfff4e080 0x0 0x100>, > + <0xff 0xfff4e180 0x0 0x680>, > + <0xff 0xfff4e800 0x0 0x600>; > + reg-names = "common", "ts", "pd", "vm"; > + clocks = <&pvt_clk>; > + /* TODO: add reset */ > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > + ao_gpio1: gpio@fffff52000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff52000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portf: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > + > + thermal-zones { > + cpu-thermal { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&pvt 0>; > + > + trips { > + trip0 { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + trip1 { > + temperature = <110000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + }; > +}; > -- > 2.34.1 > How about keeping this patch mininal? e.g only provide basic DT, cpu, clint, plic and everything up to a working serial console? Then, we probably can move out dmac, ao_gpio? thermal part, better this will easy maintainer's review job -- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li 2023-05-11 0:35 ` Yixun Lan @ 2023-05-11 0:39 ` Jisheng Zhang 2023-05-11 9:05 ` Krzysztof Kozlowski 2 siblings, 0 replies; 14+ messages in thread From: Jisheng Zhang @ 2023-05-11 0:39 UTC (permalink / raw) To: Yangtao Li Cc: Wei Fu, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Icenowy Zheng, linux-riscv, devicetree, linux-kernel On Thu, May 11, 2023 at 04:44:53AM +0800, Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Add initial device tree for the TH1520 RISC-V SoC by > T-HEAD. It's impolite to randomly jump into and take over other people's patch series. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -remove reset-sample > -convert to use thead,c900-plic > -add pvt node No, plz keep the initial soc dtsi as basic/small as possible. You can add the pvt as an independent patch. But again, don't jump into and take my patch series. > -add thermal-zones ditto > arch/riscv/boot/dts/thead/th1520.dtsi | 491 ++++++++++++++++++++++++++ > 1 file changed, 491 insertions(+) > create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > new file mode 100644 > index 000000000000..d1d94098b6bf > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -0,0 +1,491 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Alibaba Group Holding Limited. > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "thead,th1520"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <3000000>; > + > + c910_0: cpu@0 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <0>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_1: cpu@1 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <1>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_2: cpu@2 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <2>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + c910_3: cpu@3 { > + compatible = "thead,c910", "riscv"; > + device_type = "cpu"; > + riscv,isa = "rv64imafdc"; > + reg = <3>; > + i-cache-block-size = <64>; > + i-cache-size = <65536>; > + i-cache-sets = <512>; > + d-cache-block-size = <64>; > + d-cache-size = <65536>; > + d-cache-sets = <512>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&c910_0>; > + }; > + > + core1 { > + cpu = <&c910_1>; > + }; > + > + core2 { > + cpu = <&c910_2>; > + }; > + > + core3 { > + cpu = <&c910_3>; > + }; > + }; > + }; > + > + l2_cache: l2-cache { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-size = <1048576>; > + cache-sets = <1024>; > + cache-unified; > + }; > + }; > + > + osc: oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_24m"; > + #clock-cells = <0>; > + }; > + > + osc_32k: 32k-oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_32k"; > + #clock-cells = <0>; > + }; > + > + apb_clk: apb-clk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "apb_clk"; > + #clock-cells = <0>; > + }; > + > + uart_sclk: uart-sclk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "uart_sclk"; > + #clock-cells = <0>; > + }; > + > + pvt_clk: pvt-clock { > + compatible = "fixed-clock"; > + clock-frequency = <73728000>; > + clock-output-names = "pvt_clk"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + plic: interrupt-controller@ffd8000000 { > + compatible = "thead,c900-plic"; > + reg = <0xff 0xd8000000 0x0 0x01000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>; > + interrupt-controller; > + #interrupt-cells = <2>; > + riscv,ndev = <240>; > + > + }; > + > + clint: timer@ffdc000000 { > + compatible = "thead,c900-clint"; > + reg = <0xff 0xdc000000 0x0 0x00010000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>; > + }; > + > + uart0: serial@ffe7014000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7014000 0x0 0x4000>; > + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: serial@ffe7f00000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f00000 0x0 0x4000>; > + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@ffe7f04000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xe7f04000 0x0 0x4000>; > + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + gpio2: gpio@ffe7f34000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f34000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portc: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio3: gpio@ffe7f38000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xe7f38000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portd: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio0: gpio@ffec005000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec005000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porta: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + gpio1: gpio@ffec006000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xec006000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + uart2: serial@ffec010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xec010000 0x0 0x4000>; > + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + dmac0: dma-controller@ffefc00000 { > + compatible = "snps,axi-dma-1.01a"; > + reg = <0xff 0xefc00000 0x0 0x1000>; > + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&apb_clk>, <&apb_clk>; > + clock-names = "core-clk", "cfgr-clk"; > + #dma-cells = <1>; > + dma-channels = <4>; > + snps,block-size = <65536 65536 65536 65536>; > + snps,priority = <0 1 2 3>; > + snps,dma-masters = <1>; > + snps,data-width = <4>; > + snps,axi-max-burst-len = <16>; > + status = "disabled"; > + }; > + > + timer0: timer@ffefc32000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer1: timer@ffefc32014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer2: timer@ffefc32028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc32028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer3: timer@ffefc3203c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xefc3203c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + uart4: serial@fff7f08000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f08000 0x0 0x4000>; > + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart5: serial@fff7f0c000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xff 0xf7f0c000 0x0 0x4000>; > + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uart_sclk>; > + clock-names = "baudclk"; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + timer4: timer@ffffc33000 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33000 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer5: timer@ffffc33014 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33014 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer6: timer@ffffc33028 { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc33028 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + timer7: timer@ffffc3303c { > + compatible = "snps,dw-apb-timer"; > + reg = <0xff 0xffc3303c 0x0 0x14>; > + clocks = <&apb_clk>; > + clock-names = "timer"; > + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + ao_gpio0: gpio@fffff41000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff41000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + porte: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + pvt: pvt@fffff4e000 { > + compatible = "moortec,mr75203"; > + reg = <0xff 0xfff4e000 0x0 0x80>, > + <0xff 0xfff4e080 0x0 0x100>, > + <0xff 0xfff4e180 0x0 0x680>, > + <0xff 0xfff4e800 0x0 0x600>; > + reg-names = "common", "ts", "pd", "vm"; > + clocks = <&pvt_clk>; > + /* TODO: add reset */ > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > + ao_gpio1: gpio@fffff52000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0xff 0xfff52000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + portf: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + }; > + > + thermal-zones { > + cpu-thermal { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&pvt 0>; > + > + trips { > + trip0 { > + temperature = <85000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + trip1 { > + temperature = <110000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + }; > + }; > +}; > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li 2023-05-11 0:35 ` Yixun Lan 2023-05-11 0:39 ` Jisheng Zhang @ 2023-05-11 9:05 ` Krzysztof Kozlowski 2 siblings, 0 replies; 14+ messages in thread From: Krzysztof Kozlowski @ 2023-05-11 9:05 UTC (permalink / raw) To: Yangtao Li, Jisheng Zhang, Wei Fu, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: Icenowy Zheng, linux-riscv, devicetree, linux-kernel On 10/05/2023 22:44, Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Add initial device tree for the TH1520 RISC-V SoC by > T-HEAD. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -remove reset-sample > -convert to use thead,c900-plic > -add pvt node > -add thermal-zones > arch/riscv/boot/dts/thead/th1520.dtsi | 491 ++++++++++++++++++++++++++ > 1 file changed, 491 insertions(+) > create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > new file mode 100644 > index 000000000000..d1d94098b6bf > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -0,0 +1,491 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2021 Alibaba Group Holding Limited. > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "thead,th1520"; Again - missing bindings. You already got such comments, right? And still there is only one patch here - 2/5 - without anything else. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li @ 2023-05-10 20:44 ` Yangtao Li 2023-05-11 0:42 ` Yixun Lan 2023-05-11 9:12 ` Krzysztof Kozlowski 2023-05-10 20:44 ` [PATCH v2 4/5] riscv: defconfig: Enable the T-HEAD SoC Yangtao Li ` (2 subsequent siblings) 4 siblings, 2 replies; 14+ messages in thread From: Yangtao Li @ 2023-05-10 20:44 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Wei Fu, Yangtao Li Cc: Icenowy Zheng, devicetree, linux-riscv, linux-kernel From: Jisheng Zhang <jszhang@kernel.org> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Cc: Icenowy Zheng <uwu@icenowy.me> Cc: Wei Fu <wefu@redhat.com> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Yangtao Li <frank.li@vivo.com> --- v2: -cleanup `light` arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 33 ++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y += allwinner subdir-y += sifive subdir-y += starfive +subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..bc5f8677d546 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..86d677175feb --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree 2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li @ 2023-05-11 0:42 ` Yixun Lan 2023-05-11 9:12 ` Krzysztof Kozlowski 1 sibling, 0 replies; 14+ messages in thread From: Yixun Lan @ 2023-05-11 0:42 UTC (permalink / raw) To: Yangtao Li Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Wei Fu, Icenowy Zheng, devicetree, linux-riscv, linux-kernel Hi Yangtao: On 04:44 Thu 11 May , Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core > module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add > minimal device tree files for the core module and the development > board. > > Support basic uart/gpio/dmac drivers, so supports booting to a basic > shell. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -cleanup `light` > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/thead/Makefile | 2 + > .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++ > .../boot/dts/thead/th1520-lichee-pi-4a.dts | 33 ++++++++++++++++ > 4 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/thead/Makefile > create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index f0d9f89054f8..1e884868ccba 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -2,6 +2,7 @@ > subdir-y += allwinner > subdir-y += sifive > subdir-y += starfive > +subdir-y += thead > subdir-y += canaan > subdir-y += microchip > subdir-y += renesas > diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile > new file mode 100644 > index 000000000000..e311fc9a5939 > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > new file mode 100644 > index 000000000000..bc5f8677d546 > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +/dts-v1/; > + > +#include "th1520.dtsi" > + > +/ { > + model = "Sipeed Lichee Module 4A"; > + compatible = "sipeed,lichee-module-4a", "thead,th1520"; we should have these compatibles documented, so a DT-Binding should go first > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x2 0x00000000>; > + }; > +}; > + > +&osc { > + clock-frequency = <24000000>; > +}; > + > +&osc_32k { > + clock-frequency = <32768>; > +}; > + > +&apb_clk { > + clock-frequency = <62500000>; > +}; > + > +&uart_sclk { > + clock-frequency = <100000000>; > +}; for all the above clock-frequency, if it's a real fixed one - so should all hardware be the same? then probably moving them to th1520.dtsi would be better? > + > +&dmac0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > new file mode 100644 > index 000000000000..86d677175feb > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +#include "th1520-lichee-module-4a.dtsi" > + > +/ { > + model = "Sipeed Lichee Pi 4A"; > + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ditto > + > + aliases { > + gpio0 = &gpio0; > + gpio1 = &gpio1; > + gpio2 = &gpio2; > + gpio3 = &gpio3; > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > -- > 2.34.1 > -- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree 2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li 2023-05-11 0:42 ` Yixun Lan @ 2023-05-11 9:12 ` Krzysztof Kozlowski 1 sibling, 0 replies; 14+ messages in thread From: Krzysztof Kozlowski @ 2023-05-11 9:12 UTC (permalink / raw) To: Yangtao Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Wei Fu Cc: Icenowy Zheng, devicetree, linux-riscv, linux-kernel On 10/05/2023 22:44, Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core > module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add > minimal device tree files for the core module and the development > board. > > Support basic uart/gpio/dmac drivers, so supports booting to a basic > shell. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -cleanup `light` > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/thead/Makefile | 2 + > .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++ > .../boot/dts/thead/th1520-lichee-pi-4a.dts | 33 ++++++++++++++++ > 4 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/thead/Makefile > create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index f0d9f89054f8..1e884868ccba 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -2,6 +2,7 @@ > subdir-y += allwinner > subdir-y += sifive > subdir-y += starfive > +subdir-y += thead > subdir-y += canaan > subdir-y += microchip > subdir-y += renesas > diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile > new file mode 100644 > index 000000000000..e311fc9a5939 > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > new file mode 100644 > index 000000000000..bc5f8677d546 > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +/dts-v1/; > + > +#include "th1520.dtsi" > + > +/ { > + model = "Sipeed Lichee Module 4A"; > + compatible = "sipeed,lichee-module-4a", "thead,th1520"; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x2 0x00000000>; > + }; > +}; > + > +&osc { > + clock-frequency = <24000000>; > +}; > + > +&osc_32k { > + clock-frequency = <32768>; > +}; > + > +&apb_clk { > + clock-frequency = <62500000>; > +}; > + > +&uart_sclk { > + clock-frequency = <100000000>; > +}; > + > +&dmac0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > new file mode 100644 > index 000000000000..86d677175feb > --- /dev/null > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com> > + */ > + > +#include "th1520-lichee-module-4a.dtsi" > + > +/ { > + model = "Sipeed Lichee Pi 4A"; > + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; Missing bindings. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/5] riscv: defconfig: Enable the T-HEAD SoC 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li 2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li @ 2023-05-10 20:44 ` Yangtao Li 2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li 2023-05-10 23:49 ` [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yixun Lan 4 siblings, 0 replies; 14+ messages in thread From: Yangtao Li @ 2023-05-10 20:44 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: Yangtao Li, Icenowy Zheng, Wei Fu, linux-riscv, linux-kernel Now TH1520-based boards are supported, enable the platform in our defconfig. Cc: Icenowy Zheng <uwu@icenowy.me> Cc: Wei Fu <wefu@redhat.com> Signed-off-by: Yangtao Li <frank.li@vivo.com> --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..b4d7e4556501 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -30,6 +30,7 @@ CONFIG_ARCH_RENESAS=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_THEAD=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y -- 2.34.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li ` (2 preceding siblings ...) 2023-05-10 20:44 ` [PATCH v2 4/5] riscv: defconfig: Enable the T-HEAD SoC Yangtao Li @ 2023-05-10 20:44 ` Yangtao Li 2023-05-10 20:52 ` Conor Dooley 2023-05-11 0:54 ` Yixun Lan 2023-05-10 23:49 ` [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yixun Lan 4 siblings, 2 replies; 14+ messages in thread From: Yangtao Li @ 2023-05-10 20:44 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: Jisheng Zhang, Icenowy Zheng, Wei Fu, Yangtao Li, linux-kernel, linux-riscv From: Jisheng Zhang <jszhang@kernel.org> Jisheng: I would like to temporarily maintain the T-HEAD RISC-V SoC support. Yangtao: Wei and me would like to help support and maintain too. Cc: Icenowy Zheng <uwu@icenowy.me> Cc: Wei Fu <wefu@redhat.com> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Yangtao Li <frank.li@vivo.com> --- v2: -add Yangtao and Wei MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..592769efd1d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18155,6 +18155,14 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ +RISC-V T-HEAD SoC SUPPORT +M: Jisheng Zhang <jszhang@kernel.org> +M: Wei Fu <wefu@redhat.com> +M: Yangtao Li <frank.li@vivo.com> +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> M: Jack Wang <jinpu.wang@ionos.com> -- 2.34.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC 2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li @ 2023-05-10 20:52 ` Conor Dooley 2023-05-11 0:54 ` Yixun Lan 1 sibling, 0 replies; 14+ messages in thread From: Conor Dooley @ 2023-05-10 20:52 UTC (permalink / raw) To: Yangtao Li Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Icenowy Zheng, Wei Fu, linux-kernel, linux-riscv [-- Attachment #1: Type: text/plain, Size: 561 bytes --] On Thu, May 11, 2023 at 04:44:56AM +0800, Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Jisheng: > I would like to temporarily maintain the T-HEAD RISC-V SoC support. > > Yangtao: > Wei and me would like to help support and maintain too. Great, nice to have you :) I need to point out however, that much of the feedback given to the v1 of this series has yet to be acted on. This thread on the lore archive should contain the detail: https://lore.kernel.org/all/20230507182304.2934-1-jszhang@kernel.org/ Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC 2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li 2023-05-10 20:52 ` Conor Dooley @ 2023-05-11 0:54 ` Yixun Lan 2023-05-11 5:20 ` Conor Dooley 1 sibling, 1 reply; 14+ messages in thread From: Yixun Lan @ 2023-05-11 0:54 UTC (permalink / raw) To: Yangtao Li Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Icenowy Zheng, Wei Fu, linux-kernel, linux-riscv Hi Yangtao: On 04:44 Thu 11 May , Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Jisheng: > I would like to temporarily maintain the T-HEAD RISC-V SoC support. > > Yangtao: > Wei and me would like to help support and maintain too. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > v2: > -add Yangtao and Wei > MAINTAINERS | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7e0b87d5aa2e..592769efd1d1 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -18155,6 +18155,14 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ > F: Documentation/devicetree/bindings/riscv/ > F: arch/riscv/boot/dts/ > > +RISC-V T-HEAD SoC SUPPORT > +M: Jisheng Zhang <jszhang@kernel.org> > +M: Wei Fu <wefu@redhat.com> > +M: Yangtao Li <frank.li@vivo.com> > +L: linux-riscv@lists.infradead.org > +S: Maintained > +F: arch/riscv/boot/dts/thead/ > + > RNBD BLOCK DRIVERS > M: Md. Haris Iqbal <haris.iqbal@ionos.com> > M: Jack Wang <jinpu.wang@ionos.com> > -- > 2.34.1 > Don't get yourself wrong, no objection personally.. But as I saw, none of contributors has affinity with T-Head, so no idea how this will work well.. always better to take over maintainership after show enough commitment.. Anyway, raise your comments, and I'd more than happy to be proved I'm wrong -- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC 2023-05-11 0:54 ` Yixun Lan @ 2023-05-11 5:20 ` Conor Dooley 0 siblings, 0 replies; 14+ messages in thread From: Conor Dooley @ 2023-05-11 5:20 UTC (permalink / raw) To: Yixun Lan, Yangtao Li Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Icenowy Zheng, Wei Fu, linux-kernel, linux-riscv On 11 May 2023 01:54:19 IST, Yixun Lan <dlan@gentoo.org> wrote: >Hi Yangtao: > >On 04:44 Thu 11 May , Yangtao Li wrote: >> From: Jisheng Zhang <jszhang@kernel.org> >> >> Jisheng: >> I would like to temporarily maintain the T-HEAD RISC-V SoC support. >> >> Yangtao: >> Wei and me would like to help support and maintain too. >> >> Cc: Icenowy Zheng <uwu@icenowy.me> >> Cc: Wei Fu <wefu@redhat.com> >> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> >> Signed-off-by: Yangtao Li <frank.li@vivo.com> >> --- >> v2: >> -add Yangtao and Wei >> MAINTAINERS | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 7e0b87d5aa2e..592769efd1d1 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -18155,6 +18155,14 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ >> F: Documentation/devicetree/bindings/riscv/ >> F: arch/riscv/boot/dts/ >> >> +RISC-V T-HEAD SoC SUPPORT >> +M: Jisheng Zhang <jszhang@kernel.org> >> +M: Wei Fu <wefu@redhat.com> >> +M: Yangtao Li <frank.li@vivo.com> >> +L: linux-riscv@lists.infradead.org >> +S: Maintained >> +F: arch/riscv/boot/dts/thead/ >> + >> RNBD BLOCK DRIVERS >> M: Md. Haris Iqbal <haris.iqbal@ionos.com> >> M: Jack Wang <jinpu.wang@ionos.com> >> -- >> 2.34.1 >> > >Don't get yourself wrong, no objection personally.. > >But as I saw, none of contributors has affinity with T-Head, so no idea how this will >work well.. always better to take over maintainership after show enough commitment.. > >Anyway, raise your comments, and I'd more than happy to be proved I'm wrong > They're more than welcome to be the maintainers IMO. Being the vendor is no guarantee of commitment either! Guo Ren, who does work for T-Head, was the one who suggested that Wei Fu would be a good person to add here. If they don't end up maintaining it, it'll fall back to me anyway & I'd prefer to give people a chance. Thanks, Conor. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li ` (3 preceding siblings ...) 2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li @ 2023-05-10 23:49 ` Yixun Lan 4 siblings, 0 replies; 14+ messages in thread From: Yixun Lan @ 2023-05-10 23:49 UTC (permalink / raw) To: Yangtao Li Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Jisheng Zhang, Icenowy Zheng, Wei Fu, linux-riscv, linux-kernel HI Yangtao: On 04:44 Thu 11 May , Yangtao Li wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > The first SoC in the T-HEAD series is light(a.k.a th1520), containing > quad T-HEAD C910 cores. > > Cc: Icenowy Zheng <uwu@icenowy.me> > Cc: Wei Fu <wefu@redhat.com> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Yangtao Li <frank.li@vivo.com> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 1cf69f958f10..ce10a38dff37 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -41,6 +41,12 @@ config ARCH_SUNXI > This enables support for Allwinner sun20i platform hardware, > including boards based on the D1 and D1s SoCs. > > +config ARCH_THEAD > + bool "T-HEAD RISC-V SoCs" > + select ERRATA_THEAD > + help > + This enables support for the RISC-V based T-HEAD SoCs. This help section is a little bit short.. better to provide more information about the T-Head's SoC series you want to cover? > + > config ARCH_VIRT > def_bool SOC_VIRT > > -- > 2.34.1 > It would be great to have a cover letter for this series plus having an overall history changes Just curious, so you've taked to Jisheng, to take over this series? and will do follow-up version bump? -- Yixun Lan (dlan) Gentoo Linux Developer GPG Key ID AABEFD55 ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-05-11 9:12 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li 2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li 2023-05-11 0:35 ` Yixun Lan 2023-05-11 0:39 ` Jisheng Zhang 2023-05-11 9:05 ` Krzysztof Kozlowski 2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li 2023-05-11 0:42 ` Yixun Lan 2023-05-11 9:12 ` Krzysztof Kozlowski 2023-05-10 20:44 ` [PATCH v2 4/5] riscv: defconfig: Enable the T-HEAD SoC Yangtao Li 2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li 2023-05-10 20:52 ` Conor Dooley 2023-05-11 0:54 ` Yixun Lan 2023-05-11 5:20 ` Conor Dooley 2023-05-10 23:49 ` [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yixun Lan
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