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From: Bjorn Helgaas <helgaas@kernel.org>
To: Peter Geis <pgwipeout@gmail.com>
Cc: Vincenzo Palazzo <vincenzopalazzodev@gmail.com>,
	linux-pci@vger.kernel.org, robh@kernel.org, heiko@sntech.de,
	kw@linux.com, shawn.lin@rock-chips.com,
	linux-kernel@vger.kernel.org, lgirdwood@gmail.com,
	linux-rockchip@lists.infradead.org, broonie@kernel.org,
	bhelgaas@google.com,
	linux-kernel-mentees@lists.linuxfoundation.org,
	lpieralisi@kernel.org, linux-arm-kernel@lists.infradead.org,
	Dan Johansen <strit@manjaro.org>
Subject: Re: [PATCH v1] drivers: pci: introduce configurable delay for Rockchip PCIe bus scan
Date: Wed, 10 May 2023 15:47:58 -0500	[thread overview]
Message-ID: <ZFwC/seTfSoaLn0v@bhelgaas> (raw)
In-Reply-To: <CAMdYzYp6=mYSoUHN3TEXVSMbRt1HpRm0X_4RMez09V0XzQewaw@mail.gmail.com>

On Tue, May 09, 2023 at 08:11:29PM -0400, Peter Geis wrote:
> On Tue, May 9, 2023 at 5:19 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Tue, May 09, 2023 at 05:39:12PM +0200, Vincenzo Palazzo wrote:
> > > Add a configurable delay to the Rockchip PCIe driver to address
> > > crashes that occur on some old devices, such as the Pine64 RockPro64.
> > >
> > > This issue is affecting the ARM community, but there is no
> > > upstream solution for it yet.
> >
> > It sounds like this happens with several endpoints, right?  And I
> > assume the endpoints work fine in other non-Rockchip systems?  If
> > that's the case, my guess is the problem is with the Rockchip host
> > controller and how it's initialized, not with the endpoints.
> > ...

> The main issue with the rk3399 is the PCIe controller is buggy and
> triggers a SoC panic when certain error conditions occur that should
> be handled gracefully. One of those conditions is when an endpoint
> requests an access to wait and retry later.

I assume this refers to a Completion with Request Retry Status (RRS)?

> Many years ago we ran that issue to ground and with Robin Murphy's
> help we found that while it's possible to gracefully handle that
> condition it required hijacking the entire arm64 error handling
> routine. Not exactly scalable for just one SoC.

Do you have a pointer to that discussion?  The URL might save
repeating the whole exercise and could be useful for the commit log
when we try to resolve this.

> The configurable waits allow us to program reasonable times for
> 90% of the endpoints that come up in the normal amount of time, while
> being able to adjust it for the other 10% that do not. Some require
> multiple seconds before they return without error. Part of the reason
> we don't want to hardcode the wait time is because the probe isn't
> handled asynchronously, so the kernel appears to hang while waiting
> for the timeout.

Is there some way for users to figure out that they would need this
property?  Or is it just "if your kernel panics on boot, try
adding or increasing "bus-scan-delay-ms" in your DT?

Bjorn

  parent reply	other threads:[~2023-05-10 20:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-09 15:39 [PATCH v1] drivers: pci: introduce configurable delay for Rockchip PCIe bus scan Vincenzo Palazzo
2023-05-09 21:19 ` Bjorn Helgaas
2023-05-10  0:11   ` Peter Geis
2023-05-10 11:16     ` Vincenzo Palazzo
2023-05-10 19:46       ` Peter Geis
2023-05-10 20:47     ` Bjorn Helgaas [this message]
2023-05-11  1:07       ` Peter Geis
2023-05-12 10:46         ` Vincenzo Palazzo
2023-05-13  1:24           ` Bjorn Helgaas
2023-05-13 11:40             ` Peter Geis
2023-05-15 11:04               ` Vincenzo Palazzo
2023-05-15 16:51               ` Bjorn Helgaas
2023-05-15 20:52                 ` Peter Geis
2023-07-12 15:42               ` Vincenzo Palazzo
2023-05-10 11:35   ` Vincenzo Palazzo
2023-05-12 16:40   ` Vincenzo Palazzo
2023-05-10  7:57 ` Greg KH
2023-05-10 10:49   ` Vincenzo Palazzo
2023-11-20  4:15 ` Tom Fitzhenry
  -- strict thread matches above, loose matches on Subject: below --
2023-05-01 20:14 Vincenzo Palazzo

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