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From: Jason Gunthorpe <jgg@nvidia.com>
To: Michael Shavit <mshavit@google.com>
Cc: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	jean-philippe@linaro.org, nicolinc@nvidia.com,
	baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org,
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 0/5] Add PASID support to SMMUv3 unmanaged domains
Date: Wed, 10 May 2023 18:10:51 -0300	[thread overview]
Message-ID: <ZFwIWz8kBL+bti1m@nvidia.com> (raw)
In-Reply-To: <20230510205054.2667898-1-mshavit@google.com>

On Thu, May 11, 2023 at 04:50:47AM +0800, Michael Shavit wrote:
> Hi all,
> 
> This patch series refactors the arm-smmu-v3 driver and implements the
> set_dev_pasid functionality for DMA and UNMANAGED iommu domains. As part
> of this effort, we also refactor the arm-smmu-v3 driver such that each
> iommu domain represent a single address space. In particular, stage 1
> domains hold a single ContextDescriptor instead of the entire STE entry.

I'm not sure what you mean "holds" a ContextDescriptor?

Ideally the iommu_domain should only hold a pointer to some table
top. Depending on the domain type this would be a S1 IOPTE table, S2
IOPTE table or a CD table. Plus the non-table domains like IDENTITY
and blocked.

Logically when an iommu_domain is attached to a device or a PASID a
STE or CD is generated from the iommu_domain's configuration but the
iommu_domain doesn't "hold" it

When a kernel-owned CD table is used it should be held someplace else,
certianly not in the iommu_domain. Logically as a per-device
structure, but maybe with optimizations for sharing.

> The refactor is arguably valuable independently from the set_dev_pasid
> feature since an iommu_domain is conceptually closer to a single address
> space than an entire STE. In addition this unlocks some nice clean-up of
> the arm SVA implementation which today piggybacks SVA domains on the
> "primary" domain.

I always thought of this as sort of a pre-calculation of the STE, that
gets cached in the iommu_domain? Not sure the pre-calculation is that
valuable though..
 
> path forward for set_dev_pasid support? Or could a uAPI that only
> exposes a single CD instead of the entire STE be an appropriate fit for
> the nesting use cases?

The uAPI is to create an iommu_domain that holds a CD Table Top
located in user memory, it cannot deviate from this. These kinds of
iommu_domain's can only be pointed at by STEs.

Again it doesnt really "hold" the STE, but we can compute a STE that
points to the SD Table that it does hold.

Other than this, it is good to take this project on, getting PASID
support aligned with the new API is something that needs to be done
here!

Thanks,
Jason

  parent reply	other threads:[~2023-05-10 21:11 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-10 20:50 [PATCH v1 0/5] Add PASID support to SMMUv3 unmanaged domains Michael Shavit
2023-05-10 20:50 ` [PATCH v1 1/5] iommu/arm-smmu-v3: Move cdtable to arm_smmu_master Michael Shavit
2023-05-10 21:15   ` Jason Gunthorpe
2023-05-11 16:27     ` Michael Shavit
2023-05-10 20:50 ` [PATCH v1 2/5] iommu/arm-smmu-v3: Add has_stage1 field Michael Shavit
2023-05-10 20:50 ` [PATCH v1 3/5] iommu/arm-smmu-v3: Simplify arm_smmu_enable_ats Michael Shavit
2023-05-10 20:50 ` [PATCH v1 4/5] iommu/arm-smmu-v3: Keep track of attached ssids Michael Shavit
2023-05-10 21:24   ` Jason Gunthorpe
2023-05-11 15:26     ` Michael Shavit
2023-05-11 19:59       ` Jean-Philippe Brucker
2023-05-23  7:57         ` Michael Shavit
2023-05-10 23:23   ` kernel test robot
2023-05-10 20:50 ` [PATCH v1 5/5] iommu/arm-smmu-v3: Implement set_dev_pasid Michael Shavit
2023-05-10 21:10 ` Jason Gunthorpe [this message]
2023-05-11  3:52   ` [PATCH v1 0/5] Add PASID support to SMMUv3 unmanaged domains Michael Shavit
2023-05-11  4:33     ` Jason Gunthorpe
2023-05-11 12:33       ` Robin Murphy
2023-05-11 15:54         ` Jason Gunthorpe

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