From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 212E4C7EE2C for ; Wed, 24 May 2023 22:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238335AbjEXWgo (ORCPT ); Wed, 24 May 2023 18:36:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237763AbjEXWgk (ORCPT ); Wed, 24 May 2023 18:36:40 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 760EAE66 for ; Wed, 24 May 2023 15:36:14 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba83fed5097so3191074276.2 for ; Wed, 24 May 2023 15:36:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684967773; x=1687559773; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=iwTndVYq1t6b9qeOkldCRAlHVQC8rU6fAi10eJnGMhY=; b=S9ACP77jUWIZBGBDJOUQdJpybmEb6sA22nRSGa9bZhQssdnPjuMRgeJI+B1kmVifgW 2IRt4po11RHWP4h5g5HFNFjSgWFINJjidtXKmPlKISANbKSTrOGthVG9QFDotD/I/zbd TN7+1cQxG74QrKYoIhj/OYDGJnAfF+g4tNVg43fWjg0R5zWp9Ahw31noVjMVtrFTCpwY fB5IOC7tsIDoyF4MByKeQj0kj1k0isnlI0wc8FJ4V0HIqmzfxvz4UQRuQILYHyjlRG9A Q66UOgGJFKnOhtG+FKztkblHCrLTwy0c/Q+QiEzwQ44dqskMy1gpgrhPwf4pGEn76T2L fr6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684967773; x=1687559773; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=iwTndVYq1t6b9qeOkldCRAlHVQC8rU6fAi10eJnGMhY=; b=AjqvXbrlEVNSolxHHORPj0vvOP6vqcpvb9pDRP8EXTXUjOVE/TLy+YqWs0h88Rrlk/ lD0AFB3sMurkoVRNvu4SERkvfzS5Av4LJAc41TlJFX0WK0bLdo+7JZv9BEUEBGDFaVS3 tJZMWLLfJPlrdF1b1wJvgpzhY+ksjG9IHg7DyumGNtvddl+RXGkfObRJBUvlDz7NsZTU PjMe6cH9eNiwYhbQ1C2Hee6HeZnVsfb5/4kIesdgqXYMfsdkr2gJlBxhPRlM5InEPQDN B81hVu6flQdrrxq5BIeXnQ4BLRwvcY1ezwJ1xEUXISK+oH7l60UAnqMOijCEvsy55PRD JS9Q== X-Gm-Message-State: AC+VfDwWtuqaqCWoVNU6K0xcgbpnOF/7jsC1V1+23KoTgdc2zwx3CN9g gQWP8UhFbEj9/Q6cENXd4n1FCVTVMGY= X-Google-Smtp-Source: ACHHUZ6rfhhJk7Tf+97ZI8d7MguU8CMY3Qta23pVl/derDf1QpH1rs5Rs8eKZZnMfUc2basJYgKWkjLBSmY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a5b:38e:0:b0:ba8:797c:9bc7 with SMTP id k14-20020a5b038e000000b00ba8797c9bc7mr787216ybp.11.1684967773335; Wed, 24 May 2023 15:36:13 -0700 (PDT) Date: Wed, 24 May 2023 15:36:11 -0700 In-Reply-To: <20230323072714.82289-3-likexu@tencent.com> Mime-Version: 1.0 References: <20230323072714.82289-1-likexu@tencent.com> <20230323072714.82289-3-likexu@tencent.com> Message-ID: Subject: Re: [PATCH 2/7] KVM: selftests: Test Intel PMU architectural events on fixed counters From: Sean Christopherson To: Like Xu Cc: Paolo Bonzini , Jinrong Liang , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 23, 2023, Like Xu wrote: > From: Jinrong Liang > > Update test to cover Intel PMU architectural events on fixed counters. > Per Intel SDM, PMU users can also count architecture performance events > on fixed counters (specifically, FIXED_CTR0 for the retired instructions > and FIXED_CTR1 for cpu core cycles event). Therefore, if guest's CPUID > indicates that an architecture event is not available, the corresponding > fixed counter will also not count that event. > > Co-developed-by: Like Xu > Signed-off-by: Like Xu > Signed-off-by: Jinrong Liang > --- > .../selftests/kvm/x86_64/pmu_cpuid_test.c | 37 +++++++++++++++++-- > 1 file changed, 33 insertions(+), 4 deletions(-) > > diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c > index faab0a91e191..75434aa2a0ec 100644 > --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c > +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c > @@ -25,6 +25,9 @@ > #define GP_CTR_NUM_MASK GENMASK_ULL(15, GP_CTR_NUM_OFS_BIT) > #define EVT_LEN_OFS_BIT 24 > #define EVT_LEN_MASK GENMASK_ULL(31, EVT_LEN_OFS_BIT) > +#define INTEL_PMC_IDX_FIXED 32 > +#define RDPMC_FIXED_BASE BIT_ULL(30) > +#define FIXED_CTR_NUM_MASK GENMASK_ULL(4, 0) > > #define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) > > @@ -43,6 +46,14 @@ static const uint64_t arch_events[] = { > [7] = ARCH_EVENT(0xa4, 0x1), /* Topdown Slots */ > }; > > +/* Association of Fixed Counters with Architectural Performance Events */ > +static int fixed_events[] = {1, 0, 7}; > + > +static uint64_t evt_code_for_fixed_ctr(uint8_t idx) > +{ > + return arch_events[fixed_events[idx]]; > +} This appears to be more fodder for common code. > static struct kvm_vcpu *new_vcpu(void *guest_code) > { > struct kvm_vm *vm; > @@ -88,8 +99,8 @@ static bool first_uc_arg_non_zero(struct ucall *uc, void *data) > } > > static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, > - bool supported, uint32_t ctr_base_msr, > - uint64_t evt_code) > + uint8_t max_fixed_num, bool supported, > + uint32_t ctr_base_msr, uint64_t evt_code) > { > uint32_t global_msr = MSR_CORE_PERF_GLOBAL_CTRL; > unsigned int i; > @@ -108,6 +119,23 @@ static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, > GUEST_SYNC(supported == !!_rdpmc(i)); > } > > + /* No need to test independent arch events on fixed counters. */ > + if (version > 1 && max_fixed_num > 1 && > + (evt_code == evt_code_for_fixed_ctr(0) || > + evt_code == evt_code_for_fixed_ctr(1))) { > + i = (evt_code == evt_code_for_fixed_ctr(0)) ? 0 : 1; The ternary operator on top of a duplicate comparison isn't super intuitive. Maybe use gotos? Definitely just an idea, not a requirement. if (version <= 1 || max_fixed_num <= 1) goto done; if (evt_code == evt_code_for_fixed_ctr(0)) i = 0; else if (evt_code == evt_code_for_fixed_ctr(1)) i = 1; else goto done; > + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); > + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); > + wrmsr(global_msr, BIT_ULL(INTEL_PMC_IDX_FIXED + i)); > + > + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); > + > + wrmsr(global_msr, 0); > + > + GUEST_SYNC(supported == !!_rdpmc(RDPMC_FIXED_BASE | i)); > + } > + > GUEST_DONE(); > }