Re: [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs

Thierry Reding
2023-05-16T09:15:29Z

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On Thu, May 11, 2023 at 08:21:07PM +0100, Conor Dooley wrote:
> On Thu, May 11, 2023 at 04:20:49PM +0300, Peter De Schrijver wrote:
> > Add bindings for DRAM MRQ GSC support.
> >
> > Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> Perhaps Krzysztof will disagree, but looks fine to me, with some minor
> remarks below.
> Just to note, I didn't get the cover letter & therefore didn't get the
> changelog :/
> I know you had a back and forth with him about that, *my* €0.02 is that
> either you put the changelog in the cover & send it to everyone, or you
> put it in each patch.
>
> > ---
> > .../nvidia,tegra264-bpmp-shmem.yaml | 47 +++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
> > new file mode 100644
> > index 000000000000..4087459c01db
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
> > @@ -0,0 +1,47 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Tegra CPU-NS - BPMP IPC reserved memory
> > +
> > +maintainers:
> > + - Peter De Schrijver <pdeschrijver@nvidia.com>
> > +
> > +description: |
>
> You don't appear to have any formatting to preserve, so the | is not
> needed.
>
> > + Define a memory region used for communication between CPU-NS and BPMP.
> > + Typically this node is created by the bootloader as the physical address
> > + has to be known to both CPU-NS and BPMP for correct IPC operation.
> > + The memory region is defined using a child node under /reserved-memory.
> > + The sub-node is named shmem@ .
> > +
> > +allOf:
> > + - $ref: reserved-memory.yaml
> > +
> > +properties:
> > + compatible:
> > + const: nvidia,tegra264-bpmp-shmem
> > +
> > + reg:
> > + description: The physical address and size of the shared SDRAM region
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - no-map
> > +
> > +examples:
> > + - |
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> You also do not need these size/address-cells, because...
>
> > + dram_cpu_bpmp_mail: shmem@f1be0000 {
> (nit: double space ^^)
>
> > + compatible = "nvidia,tegra264-bpmp-shmem";
> > + reg = <0x0 0xf1be0000 0x0 0x2000>;
>
> ...the 64-bit registers here are both 0x0.

I think Peter had to add these explicitly because the defaults are 2 and
1, respectively, and DTC was warning about this. I suppose the "reg"
property could be adjusted to use the defaults, but on the other hand I
find that it's good if the examples match reality and we need size-cells
to be 2 on Tegra.

Either way is fine with me, though.

Thierry

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