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From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic
Date: Fri, 2 Jun 2023 16:23:48 -0700	[thread overview]
Message-ID: <ZHp6BDhcv/popAqm@google.com> (raw)
In-Reply-To: <20230530060423.32361-4-likexu@tencent.com>

On Tue, May 30, 2023, Like Xu wrote:
> From: Like Xu <likexu@tencent.com>
> 
> AMD PerfMonV2 defines three registers similar to part of the Intel
> v2 PMU registers, including the GLOBAL_CTRL, GLOBAL_STATUS and
> GLOBAL_OVF_CTRL MSRs. For better code reuse, this specific part of
> the handling can be extracted to make it generic for X86 as a straight
> code movement.
> 
> Specifically, the kvm_pmu_set/get_msr() handlers of GLOBAL_STATUS,
> GLOBAL_CTRL, GLOBAL_OVF_CTRL defined for Intel are moved to generic
> pmu.c and the callback function .pmc_is_globally_enabled is removed,
> which is very helpful to introduce the AMD PerfMonV2 code later.

Yeah, except this patch doesn't actually move anything.  *Some* of the common bits
show up in pmu.c, but the same bits in pmu_intel.c get left behind. 

> The new eponymous pmc_is_globally_enabled() works well as legacy AMD
> vPMU version is indexed as 1. Note that the specific *_is_valid_msr will
> continue to be used to avoid cross-vendor MSR access.

This should be two patches.  Moving the GLOBAL_CTRL stuff is logically separate
from moving the pmc_is_enabled() code.

> Signed-off-by: Like Xu <likexu@tencent.com>
> ---
> @@ -213,6 +212,22 @@ static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
>  	kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
>  }
>  
> +/*
> + * Check if a PMC is enabled by comparing it against global_ctrl bits.
> + *
> + * If the current version of vPMU doesn't have global_ctrl MSR,
> + * all vPMCs are enabled (return TRUE).
> + */
> +static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
> +{
> +	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
> +
> +	if (pmu->version < 2)

Nah, we're not open coding this check, not after putting in the effort to squash
the mess of open coding on Intel.  Moving intel_pmu_has_perf_global_ctrl() is
trivial, and also allows moving the existence checks into kvm_pmu_is_valid_msr().

  reply	other threads:[~2023-06-02 23:23 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30  6:04 [PATCH v6 00/10] KVM: x86: Add AMD Guest PerfMonV2 PMU support Like Xu
2023-05-30  6:04 ` [PATCH v6 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-05-30  6:04 ` [PATCH v6 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits Like Xu
2023-06-02 21:59   ` Sean Christopherson
2023-05-30  6:04 ` [PATCH v6 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-06-02 23:23   ` Sean Christopherson [this message]
2023-05-30  6:04 ` [PATCH v6 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Like Xu
2023-05-30  6:04 ` [PATCH v6 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Like Xu
2023-06-02  0:50   ` Sean Christopherson
2023-05-30  6:04 ` [PATCH v6 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-05-30  6:04 ` [PATCH v6 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Like Xu
2023-05-30  6:04 ` [PATCH v6 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Like Xu
2023-05-30  6:04 ` [PATCH v6 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-05-30  6:04 ` [PATCH v6 10/10] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu

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