[PATCH v2 0/3] perf mem amd: Fix few logic bugs

Ravi Bangoria
2023-06-15T05:17:30Z

Recent PMU refactoring changes[1] introduced a notion of core vs other
PMUs and made perf mem/c2c code depend only on core PMUs, which is
logically wrong for AMD as perf mem/c2c on AMD depends on IBS OP PMU,
not the core PMU. Although user visible perf mem/c2c functionality is
still working fine, internal code logic is wrong. Fix those.

[1] https://lore.kernel.org/r/20230527072210.2900565-1-irogers@google.com

v1: https://lore.kernel.org/r/20230613095506.547-1-ravi.bangoria@amd.com
v1->v2:
- Patch #2 of last version is already picked up by Arnaldo. So skip it.
- Scan all PMUs unconditionally in perf mem code instead of making it
conditional on arch.

Ravi Bangoria (3):
perf pmus: Describe semantics of 'core_pmus' and 'other_pmus'
perf mem amd: Fix perf_pmus__num_mem_pmus()
perf mem: Scan all PMUs instead of just core ones

tools/perf/arch/x86/util/pmu.c | 12 ++++++++++++
tools/perf/util/mem-events.c | 13 +++++++++----
tools/perf/util/pmus.c | 17 ++++++++++++++++-
3 files changed, 37 insertions(+), 5 deletions(-)

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2.40.1