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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	Mario Limonciello <mario.limonciello@amd.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Len Brown <lenb@kernel.org>,
	linux-acpi@vger.kernel.org, Iain Lane <iain@orangesquash.org.uk>,
	Kuppuswamy Sathyanarayanan 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3
Date: Wed, 12 Jul 2023 18:23:08 +0300	[thread overview]
Message-ID: <ZK7FXIA+7GTDYK+Z@smile.fi.intel.com> (raw)
In-Reply-To: <CAJZ5v0hmDVkUz8QbE3Jx0kLqDfB6hEuQjhd_u8Kjj2hyZYpZGA@mail.gmail.com>

On Wed, Jul 12, 2023 at 01:48:11PM +0200, Rafael J. Wysocki wrote:
> On Wed, Jul 12, 2023 at 12:14 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Mon, Jul 10, 2023 at 07:53:25PM -0500, Mario Limonciello wrote:

...

> > Tangent unrelated to *this* patch: I don't know how to think about the
> > pci_use_mid_pm() in platform_pci_power_manageable() because I haven't
> > seen a MID spec.  pci_use_mid_pm() isn't dependent on "dev", so we
> > claim *all* PCI devices, even external ones, are power manageable by
> > the platform, which doesn't seem right.
> 
> No, we don't.
> 
> This only means that PCI devices may be power manageable by the
> platform and so the platform code should be invoked to check that.
> AFAICS, intel_mid_pwr_get_lss_id(() will return an error for a device
> without platform PM support.

If it's a problem somewhere, we may even harden that by checking
the bus nr to be 0. The devices outside bus 0 for sure have not to
be affected by this code.

-- 
With Best Regards,
Andy Shevchenko



      reply	other threads:[~2023-07-12 15:23 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-11  0:53 [PATCH v7 0/2] Fix wakeup problems on some AMD platforms Mario Limonciello
2023-07-11  0:53 ` [PATCH v7 1/2] PCI: Refactor pci_bridge_d3_possible() Mario Limonciello
2023-07-11  0:53 ` [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3 Mario Limonciello
2023-07-11 22:14   ` Bjorn Helgaas
2023-07-11 22:54     ` Mario Limonciello
2023-07-12 12:13       ` Rafael J. Wysocki
2023-07-12 16:09         ` Limonciello, Mario
2023-07-14 19:17           ` Rafael J. Wysocki
2023-07-15  0:46             ` Limonciello, Mario
2023-08-01  3:25               ` Mario Limonciello
2023-08-01 10:15                 ` Rafael J. Wysocki
2023-08-02  3:17                   ` Mario Limonciello
2023-08-02  5:26                     ` Mika Westerberg
2023-08-02 14:10                       ` Mario Limonciello
2023-08-02 14:31                         ` Mika Westerberg
2023-08-02 14:35                           ` Mario Limonciello
2023-08-02 15:00                             ` Mika Westerberg
     [not found]             ` <67fa2dda-f383-1864-57b8-08b86263bd02@amd.com>
2023-08-01  9:54               ` Rafael J. Wysocki
2023-07-12 11:48     ` Rafael J. Wysocki
2023-07-12 15:23       ` Andy Shevchenko [this message]

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