* [PATCH 2/2] clk: imx: imx8ulp: update SPLL2 type
2023-06-25 12:33 [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan (OSS)
@ 2023-06-25 12:33 ` Peng Fan (OSS)
2023-07-25 7:39 ` Abel Vesa
2023-07-20 1:12 ` [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Peng Fan (OSS) @ 2023-06-25 12:33 UTC (permalink / raw)
To: abelvesa, mturquette, sboyd, shawnguo, s.hauer, kernel, festevam
Cc: linux-imx, linux-clk, linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
use the new type IMX_PLLV4_IMX8ULP_1GHZ.
Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8ulp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c
index e308c88cb801..1b04e2fc78ad 100644
--- a/drivers/clk/imx/clk-imx8ulp.c
+++ b/drivers/clk/imx/clk-imx8ulp.c
@@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
- clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500);
+ clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: imx: imx8ulp: update SPLL2 type
2023-06-25 12:33 ` [PATCH 2/2] clk: imx: imx8ulp: update SPLL2 type Peng Fan (OSS)
@ 2023-07-25 7:39 ` Abel Vesa
0 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2023-07-25 7:39 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: abelvesa, mturquette, sboyd, shawnguo, s.hauer, kernel, festevam,
linux-imx, linux-clk, linux-arm-kernel, linux-kernel, Peng Fan
On 23-06-25 20:33:40, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can
> support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
> use the new type IMX_PLLV4_IMX8ULP_1GHZ.
>
> Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/clk/imx/clk-imx8ulp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c
> index e308c88cb801..1b04e2fc78ad 100644
> --- a/drivers/clk/imx/clk-imx8ulp.c
> +++ b/drivers/clk/imx/clk-imx8ulp.c
> @@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
> clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
> clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
>
> - clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500);
> + clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
> clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
> clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);
>
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
2023-06-25 12:33 [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan (OSS)
2023-06-25 12:33 ` [PATCH 2/2] clk: imx: imx8ulp: update SPLL2 type Peng Fan (OSS)
@ 2023-07-20 1:12 ` Peng Fan
2023-07-25 7:39 ` Abel Vesa
2023-08-14 10:10 ` Abel Vesa
3 siblings, 0 replies; 6+ messages in thread
From: Peng Fan @ 2023-07-20 1:12 UTC (permalink / raw)
To: Peng Fan (OSS), abelvesa@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com
Cc: dl-linux-imx, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Ye Li, Jacky Bai
Hi Abel, Stephen,
> Subject: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
Would you give a look at this patchset?
Thanks,
Peng.
>
> From: Ye Li <ye.li@nxp.com>
>
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO
> from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27
> to 54, not some fixed values. If using current PLL implementation, some
> clock rate can't be supported.
>
> Fix the issue by adding new type for the SPLL2 and use MULT range to
> replace MULT table
>
> Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp")
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-pllv4.c | 46 +++++++++++++++++++++++++++++--------
> drivers/clk/imx/clk.h | 1 +
> 2 files changed, 37 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c index
> 6e7e34571fc8..9b136c951762 100644
> --- a/drivers/clk/imx/clk-pllv4.c
> +++ b/drivers/clk/imx/clk-pllv4.c
> @@ -44,11 +44,15 @@ struct clk_pllv4 {
> u32 cfg_offset;
> u32 num_offset;
> u32 denom_offset;
> + bool use_mult_range;
> };
>
> /* Valid PLL MULT Table */
> static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
>
> +/* Valid PLL MULT range, (max, min) */
> +static const int pllv4_mult_range[] = {54, 27};
> +
> #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
>
> #define LOCK_TIMEOUT_US USEC_PER_MSEC
> @@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct
> clk_hw *hw, static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned
> long rate,
> unsigned long *prate)
> {
> + struct clk_pllv4 *pll = to_clk_pllv4(hw);
> unsigned long parent_rate = *prate;
> unsigned long round_rate, i;
> u32 mfn, mfd = DEFAULT_MFD;
> bool found = false;
> u64 temp64;
> -
> - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> - round_rate = parent_rate * pllv4_mult_table[i];
> - if (rate >= round_rate) {
> + u32 mult;
> +
> + if (pll->use_mult_range) {
> + temp64 = (u64)rate;
> + do_div(temp64, parent_rate);
> + mult = temp64;
> + if (mult >= pllv4_mult_range[1] &&
> + mult <= pllv4_mult_range[0]) {
> + round_rate = parent_rate * mult;
> found = true;
> - break;
> + }
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> + round_rate = parent_rate * pllv4_mult_table[i];
> + if (rate >= round_rate) {
> + found = true;
> + break;
> + }
> }
> }
>
> @@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw
> *hw, unsigned long rate,
> return round_rate + (u32)temp64;
> }
>
> -static bool clk_pllv4_is_valid_mult(unsigned int mult)
> +static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int
> +mult)
> {
> int i;
>
> /* check if mult is in valid MULT table */
> - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> - if (pllv4_mult_table[i] == mult)
> + if (pll->use_mult_range) {
> + if (mult >= pllv4_mult_range[1] &&
> + mult <= pllv4_mult_range[0])
> return true;
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> + if (pllv4_mult_table[i] == mult)
> + return true;
> + }
> }
>
> return false;
> @@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw,
> unsigned long rate,
>
> mult = rate / parent_rate;
>
> - if (!clk_pllv4_is_valid_mult(mult))
> + if (!clk_pllv4_is_valid_mult(pll, mult))
> return -EINVAL;
>
> if (parent_rate <= MAX_MFD)
> @@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum
> imx_pllv4_type type, const char *name,
>
> pll->base = base;
>
> - if (type == IMX_PLLV4_IMX8ULP) {
> + if (type == IMX_PLLV4_IMX8ULP ||
> + type == IMX_PLLV4_IMX8ULP_1GHZ) {
> pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
> pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
> pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
> + if (type == IMX_PLLV4_IMX8ULP_1GHZ)
> + pll->use_mult_range = true;
> } else {
> pll->cfg_offset = PLL_CFG_OFFSET;
> pll->num_offset = PLL_NUM_OFFSET;
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index
> af19d9f6aed0..adb7ad649a0d 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -45,6 +45,7 @@ enum imx_pll14xx_type { enum imx_pllv4_type {
> IMX_PLLV4_IMX7ULP,
> IMX_PLLV4_IMX8ULP,
> + IMX_PLLV4_IMX8ULP_1GHZ,
> };
>
> enum imx_pfdv2_type {
> --
> 2.37.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
2023-06-25 12:33 [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan (OSS)
2023-06-25 12:33 ` [PATCH 2/2] clk: imx: imx8ulp: update SPLL2 type Peng Fan (OSS)
2023-07-20 1:12 ` [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan
@ 2023-07-25 7:39 ` Abel Vesa
2023-08-14 10:10 ` Abel Vesa
3 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2023-07-25 7:39 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: abelvesa, mturquette, sboyd, shawnguo, s.hauer, kernel, festevam,
linux-imx, linux-clk, linux-arm-kernel, linux-kernel, Ye Li,
Peng Fan, Jacky Bai
On 23-06-25 20:33:39, Peng Fan (OSS) wrote:
> From: Ye Li <ye.li@nxp.com>
>
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can
> support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
> using a range from 27 to 54, not some fixed values. If using
> current PLL implementation, some clock rate can't be supported.
>
> Fix the issue by adding new type for the SPLL2 and use MULT range
> to replace MULT table
>
> Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp")
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
LGTM.
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/clk/imx/clk-pllv4.c | 46 +++++++++++++++++++++++++++++--------
> drivers/clk/imx/clk.h | 1 +
> 2 files changed, 37 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
> index 6e7e34571fc8..9b136c951762 100644
> --- a/drivers/clk/imx/clk-pllv4.c
> +++ b/drivers/clk/imx/clk-pllv4.c
> @@ -44,11 +44,15 @@ struct clk_pllv4 {
> u32 cfg_offset;
> u32 num_offset;
> u32 denom_offset;
> + bool use_mult_range;
> };
>
> /* Valid PLL MULT Table */
> static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
>
> +/* Valid PLL MULT range, (max, min) */
> +static const int pllv4_mult_range[] = {54, 27};
> +
> #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
>
> #define LOCK_TIMEOUT_US USEC_PER_MSEC
> @@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
> static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long *prate)
> {
> + struct clk_pllv4 *pll = to_clk_pllv4(hw);
> unsigned long parent_rate = *prate;
> unsigned long round_rate, i;
> u32 mfn, mfd = DEFAULT_MFD;
> bool found = false;
> u64 temp64;
> -
> - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> - round_rate = parent_rate * pllv4_mult_table[i];
> - if (rate >= round_rate) {
> + u32 mult;
> +
> + if (pll->use_mult_range) {
> + temp64 = (u64)rate;
> + do_div(temp64, parent_rate);
> + mult = temp64;
> + if (mult >= pllv4_mult_range[1] &&
> + mult <= pllv4_mult_range[0]) {
> + round_rate = parent_rate * mult;
> found = true;
> - break;
> + }
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> + round_rate = parent_rate * pllv4_mult_table[i];
> + if (rate >= round_rate) {
> + found = true;
> + break;
> + }
> }
> }
>
> @@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
> return round_rate + (u32)temp64;
> }
>
> -static bool clk_pllv4_is_valid_mult(unsigned int mult)
> +static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
> {
> int i;
>
> /* check if mult is in valid MULT table */
> - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> - if (pllv4_mult_table[i] == mult)
> + if (pll->use_mult_range) {
> + if (mult >= pllv4_mult_range[1] &&
> + mult <= pllv4_mult_range[0])
> return true;
> + } else {
> + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> + if (pllv4_mult_table[i] == mult)
> + return true;
> + }
> }
>
> return false;
> @@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
>
> mult = rate / parent_rate;
>
> - if (!clk_pllv4_is_valid_mult(mult))
> + if (!clk_pllv4_is_valid_mult(pll, mult))
> return -EINVAL;
>
> if (parent_rate <= MAX_MFD)
> @@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
>
> pll->base = base;
>
> - if (type == IMX_PLLV4_IMX8ULP) {
> + if (type == IMX_PLLV4_IMX8ULP ||
> + type == IMX_PLLV4_IMX8ULP_1GHZ) {
> pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
> pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
> pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
> + if (type == IMX_PLLV4_IMX8ULP_1GHZ)
> + pll->use_mult_range = true;
> } else {
> pll->cfg_offset = PLL_CFG_OFFSET;
> pll->num_offset = PLL_NUM_OFFSET;
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index af19d9f6aed0..adb7ad649a0d 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -45,6 +45,7 @@ enum imx_pll14xx_type {
> enum imx_pllv4_type {
> IMX_PLLV4_IMX7ULP,
> IMX_PLLV4_IMX8ULP,
> + IMX_PLLV4_IMX8ULP_1GHZ,
> };
>
> enum imx_pfdv2_type {
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
2023-06-25 12:33 [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range Peng Fan (OSS)
` (2 preceding siblings ...)
2023-07-25 7:39 ` Abel Vesa
@ 2023-08-14 10:10 ` Abel Vesa
3 siblings, 0 replies; 6+ messages in thread
From: Abel Vesa @ 2023-08-14 10:10 UTC (permalink / raw)
To: abelvesa, mturquette, sboyd, shawnguo, s.hauer, kernel, festevam,
Peng Fan (OSS)
Cc: linux-imx, linux-clk, linux-arm-kernel, linux-kernel, Ye Li,
Peng Fan, Jacky Bai
On Sun, 25 Jun 2023 20:33:39 +0800, Peng Fan (OSS) wrote:
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can
> support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
> using a range from 27 to 54, not some fixed values. If using
> current PLL implementation, some clock rate can't be supported.
>
> Fix the issue by adding new type for the SPLL2 and use MULT range
> to replace MULT table
>
> [...]
Applied, thanks!
[1/2] clk: imx: pllv4: Fix SPLL2 MULT range
commit: 3f0cdb945471f1abd1cf4d172190e9c489c5052a
[2/2] clk: imx: imx8ulp: update SPLL2 type
commit: 7653a59be8af043adc4c09473975a860e6055ff9
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply [flat|nested] 6+ messages in thread