* [PATCH V1 0/2] Add Phy Configuration support for SC7280 @ 2023-08-16 15:48 Nitin Rawat 2023-08-16 15:48 ` [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible " Nitin Rawat 2023-08-16 15:48 ` [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support " Nitin Rawat 0 siblings, 2 replies; 11+ messages in thread From: Nitin Rawat @ 2023-08-16 15:48 UTC (permalink / raw) To: andersson, konrad.dybcio, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, Nitin Rawat This patch adds Phy configuration support for Qualcomm SC7280 SOC. Nitin Rawat (2): dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++ 2 files changed, 144 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-16 15:48 [PATCH V1 0/2] Add Phy Configuration support for SC7280 Nitin Rawat @ 2023-08-16 15:48 ` Nitin Rawat 2023-08-16 20:31 ` Dmitry Baryshkov 2023-08-18 10:34 ` Krzysztof Kozlowski 2023-08-16 15:48 ` [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support " Nitin Rawat 1 sibling, 2 replies; 11+ messages in thread From: Nitin Rawat @ 2023-08-16 15:48 UTC (permalink / raw) To: andersson, konrad.dybcio, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, Nitin Rawat Document the QMP UFS PHY compatible for SC7280. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index d981d77e82e4..ad78da9c2c1a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8450-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy + - qcom,sc7280-qmp-ufs-phy reg: maxItems: 1 @@ -110,6 +111,7 @@ allOf: - qcom,sm8250-qmp-ufs-phy - qcom,sm8350-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy + - qcom,sc7280-qmp-ufs-phy then: properties: clocks: -- 2.17.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-16 15:48 ` [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible " Nitin Rawat @ 2023-08-16 20:31 ` Dmitry Baryshkov 2023-08-17 6:49 ` Vinod Koul 2023-08-18 10:34 ` Krzysztof Kozlowski 1 sibling, 1 reply; 11+ messages in thread From: Dmitry Baryshkov @ 2023-08-16 20:31 UTC (permalink / raw) To: Nitin Rawat Cc: andersson, konrad.dybcio, vkoul, agross, kishon, linux-arm-msm, linux-phy, linux-kernel On Wed, 16 Aug 2023 at 18:50, Nitin Rawat <quic_nitirawa@quicinc.com> wrote: > > Document the QMP UFS PHY compatible for SC7280. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > index d981d77e82e4..ad78da9c2c1a 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > @@ -31,6 +31,7 @@ properties: > - qcom,sm8350-qmp-ufs-phy > - qcom,sm8450-qmp-ufs-phy > - qcom,sm8550-qmp-ufs-phy > + - qcom,sc7280-qmp-ufs-phy > > reg: > maxItems: 1 > @@ -110,6 +111,7 @@ allOf: > - qcom,sm8250-qmp-ufs-phy > - qcom,sm8350-qmp-ufs-phy > - qcom,sm8550-qmp-ufs-phy > + - qcom,sc7280-qmp-ufs-phy Please keep both lists sorted. > then: > properties: > clocks: > -- > 2.17.1 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-16 20:31 ` Dmitry Baryshkov @ 2023-08-17 6:49 ` Vinod Koul 2023-08-19 12:05 ` Nitin Rawat 0 siblings, 1 reply; 11+ messages in thread From: Vinod Koul @ 2023-08-17 6:49 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Nitin Rawat, andersson, konrad.dybcio, agross, kishon, linux-arm-msm, linux-phy, linux-kernel On 16-08-23, 23:31, Dmitry Baryshkov wrote: > On Wed, 16 Aug 2023 at 18:50, Nitin Rawat <quic_nitirawa@quicinc.com> wrote: > > > > Document the QMP UFS PHY compatible for SC7280. > > > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > > --- > > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > > index d981d77e82e4..ad78da9c2c1a 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml > > @@ -31,6 +31,7 @@ properties: > > - qcom,sm8350-qmp-ufs-phy > > - qcom,sm8450-qmp-ufs-phy > > - qcom,sm8550-qmp-ufs-phy > > + - qcom,sc7280-qmp-ufs-phy > > > > reg: > > maxItems: 1 > > @@ -110,6 +111,7 @@ allOf: > > - qcom,sm8250-qmp-ufs-phy > > - qcom,sm8350-qmp-ufs-phy > > - qcom,sm8550-qmp-ufs-phy > > + - qcom,sc7280-qmp-ufs-phy > > Please keep both lists sorted. Yes please -- ~Vinod ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-17 6:49 ` Vinod Koul @ 2023-08-19 12:05 ` Nitin Rawat 0 siblings, 0 replies; 11+ messages in thread From: Nitin Rawat @ 2023-08-19 12:05 UTC (permalink / raw) To: Vinod Koul, Dmitry Baryshkov Cc: andersson, konrad.dybcio, agross, kishon, linux-arm-msm, linux-phy, linux-kernel Hi Dmitry and Vinod, Thanks for the review. I taken care of all the comments in latest patchset I posted. Regards, Nitin On 8/17/2023 12:19 PM, Vinod Koul wrote: > On 16-08-23, 23:31, Dmitry Baryshkov wrote: >> On Wed, 16 Aug 2023 at 18:50, Nitin Rawat <quic_nitirawa@quicinc.com> wrote: >>> >>> Document the QMP UFS PHY compatible for SC7280. >>> >>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >>> --- >>> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml >>> index d981d77e82e4..ad78da9c2c1a 100644 >>> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml >>> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml >>> @@ -31,6 +31,7 @@ properties: >>> - qcom,sm8350-qmp-ufs-phy >>> - qcom,sm8450-qmp-ufs-phy >>> - qcom,sm8550-qmp-ufs-phy >>> + - qcom,sc7280-qmp-ufs-phy >>> >>> reg: >>> maxItems: 1 >>> @@ -110,6 +111,7 @@ allOf: >>> - qcom,sm8250-qmp-ufs-phy >>> - qcom,sm8350-qmp-ufs-phy >>> - qcom,sm8550-qmp-ufs-phy >>> + - qcom,sc7280-qmp-ufs-phy >> >> Please keep both lists sorted. > > Yes please > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-16 15:48 ` [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible " Nitin Rawat 2023-08-16 20:31 ` Dmitry Baryshkov @ 2023-08-18 10:34 ` Krzysztof Kozlowski 2023-08-19 12:03 ` Nitin Rawat 1 sibling, 1 reply; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-08-18 10:34 UTC (permalink / raw) To: Nitin Rawat, andersson, konrad.dybcio, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel On 16/08/2023 17:48, Nitin Rawat wrote: > Document the QMP UFS PHY compatible for SC7280. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed at least DT list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible for SC7280 2023-08-18 10:34 ` Krzysztof Kozlowski @ 2023-08-19 12:03 ` Nitin Rawat 0 siblings, 0 replies; 11+ messages in thread From: Nitin Rawat @ 2023-08-19 12:03 UTC (permalink / raw) To: Krzysztof Kozlowski, andersson, konrad.dybcio, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel Hi Krzysztof, Sorry for the inconvenience . I have addressed other reviewers comments and have resent the latest patchset to all the intended To/Cc entries. Thanks, Nitin On 8/18/2023 4:04 PM, Krzysztof Kozlowski wrote: > On 16/08/2023 17:48, Nitin Rawat wrote: >> Document the QMP UFS PHY compatible for SC7280. >> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. > > You missed at least DT list (maybe more), so this won't be tested by > automated tooling. Performing review on untested code might be a waste > of time, thus I will skip this patch entirely till you follow the > process allowing the patch to be tested. > > Please kindly resend and include all necessary To/Cc entries. > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 2023-08-16 15:48 [PATCH V1 0/2] Add Phy Configuration support for SC7280 Nitin Rawat 2023-08-16 15:48 ` [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible " Nitin Rawat @ 2023-08-16 15:48 ` Nitin Rawat 2023-08-16 18:12 ` Konrad Dybcio 2023-08-16 20:30 ` Dmitry Baryshkov 1 sibling, 2 replies; 11+ messages in thread From: Nitin Rawat @ 2023-08-16 15:48 UTC (permalink / raw) To: andersson, konrad.dybcio, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, Nitin Rawat, Manish Pandey Add SC7280 specific register layout and table configs. Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 03cd47faf3fd..c5ab5f0792f5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -493,6 +493,70 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; +static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6D), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0A), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1F), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xFF), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xD8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xAA), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), +}; + static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), }; @@ -521,6 +585,47 @@ static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), }; +static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -1162,6 +1267,40 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .regs = ufsphy_v6_regs_layout, }; +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sc7280_ufsphy_tx, + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), + .rx = sc7280_ufsphy_rx, + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), + .pcs = sc7280_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8250_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx = sc7280_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = ufsphy_v4_regs_layout, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, @@ -1682,6 +1821,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { }, { .compatible = "qcom,sm8550-qmp-ufs-phy", .data = &sm8550_ufsphy_cfg, + }, { + .compatible = "qcom,sc7280-qmp-ufs-phy", + .data = &sc7280_ufsphy_cfg, }, { }, }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 2023-08-16 15:48 ` [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support " Nitin Rawat @ 2023-08-16 18:12 ` Konrad Dybcio 2023-08-16 18:13 ` Konrad Dybcio 2023-08-16 20:30 ` Dmitry Baryshkov 1 sibling, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2023-08-16 18:12 UTC (permalink / raw) To: Nitin Rawat, andersson, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, Manish Pandey On 16.08.2023 17:48, Nitin Rawat wrote: > Add SC7280 specific register layout and table configs. > > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- Looks very reasonable compared to what I can see downstream. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 2023-08-16 18:12 ` Konrad Dybcio @ 2023-08-16 18:13 ` Konrad Dybcio 0 siblings, 0 replies; 11+ messages in thread From: Konrad Dybcio @ 2023-08-16 18:13 UTC (permalink / raw) To: Nitin Rawat, andersson, vkoul, agross, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, Manish Pandey On 16.08.2023 20:12, Konrad Dybcio wrote: > On 16.08.2023 17:48, Nitin Rawat wrote: >> Add SC7280 specific register layout and table configs. >> >> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- > Looks very reasonable compared to what I can see downstream. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> I guess one nit I'd add is that having the compatible list sorted alphanumerically would be a nice touch Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280 2023-08-16 15:48 ` [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support " Nitin Rawat 2023-08-16 18:12 ` Konrad Dybcio @ 2023-08-16 20:30 ` Dmitry Baryshkov 1 sibling, 0 replies; 11+ messages in thread From: Dmitry Baryshkov @ 2023-08-16 20:30 UTC (permalink / raw) To: Nitin Rawat Cc: andersson, konrad.dybcio, vkoul, agross, kishon, linux-arm-msm, linux-phy, linux-kernel, Manish Pandey On Wed, 16 Aug 2023 at 18:50, Nitin Rawat <quic_nitirawa@quicinc.com> wrote: > > Add SC7280 specific register layout and table configs. > > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 03cd47faf3fd..c5ab5f0792f5 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -493,6 +493,70 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), > }; > > +static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), > +}; > + > +static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), > +}; > + > +static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6D), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0A), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1F), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xFF), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xD8), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xAA), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), > + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), > +}; > + > static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), > }; > @@ -521,6 +585,47 @@ static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), > }; > > +static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { Please put this next to sc7280 register arrays. > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), > +}; > + > static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), > @@ -1162,6 +1267,40 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > .regs = ufsphy_v6_regs_layout, > }; > > +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { This should come before sc8280xp entry. > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets, > + > + .tbls = { > + .serdes = sm8150_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), > + .tx = sc7280_ufsphy_tx, > + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), > + .rx = sc7280_ufsphy_rx, > + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), > + .pcs = sc7280_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), > + }, > + .tbls_hs_b = { > + .serdes = sm8150_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), > + }, > + .tbls_hs_g4 = { > + .tx = sm8250_ufsphy_hs_g4_tx, > + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), > + .rx = sc7280_ufsphy_hs_g4_rx, > + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), > + .pcs = sm8150_ufsphy_hs_g4_pcs, > + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), > + }, > + .clk_list = sm8450_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = ufsphy_v4_regs_layout, > +}; > + > static void qmp_ufs_configure_lane(void __iomem *base, > const struct qmp_phy_init_tbl tbl[], > int num, > @@ -1682,6 +1821,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > }, { > .compatible = "qcom,sm8550-qmp-ufs-phy", > .data = &sm8550_ufsphy_cfg, > + }, { > + .compatible = "qcom,sc7280-qmp-ufs-phy", > + .data = &sc7280_ufsphy_cfg, This list is sorted, please put new data to the proper place. > }, > { }, > }; > -- > 2.17.1 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-08-19 12:06 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-16 15:48 [PATCH V1 0/2] Add Phy Configuration support for SC7280 Nitin Rawat 2023-08-16 15:48 ` [PATCH V1 1/2] dt-bindings: phy: Add QMP UFS PHY comptible " Nitin Rawat 2023-08-16 20:31 ` Dmitry Baryshkov 2023-08-17 6:49 ` Vinod Koul 2023-08-19 12:05 ` Nitin Rawat 2023-08-18 10:34 ` Krzysztof Kozlowski 2023-08-19 12:03 ` Nitin Rawat 2023-08-16 15:48 ` [PATCH V1 2/2] phy: qcom-qmp-ufs: Add Phy Configuration support " Nitin Rawat 2023-08-16 18:12 ` Konrad Dybcio 2023-08-16 18:13 ` Konrad Dybcio 2023-08-16 20:30 ` Dmitry Baryshkov
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