Re: [PATCH v2 1/2] iommu/arm-smmu-v3: Add support for ECMDQ register mode

[Nicolin Chen <nicolinc@nvidia.com>]

Hi Zhen,

On Wed, Aug 09, 2023 at 06:13:02AM -0700, thunder.leizhen@huaweicloud.com wrote:
> +static int arm_smmu_ecmdq_layout(struct arm_smmu_device *smmu)
> +{
> +       int cpu;
> +       struct arm_smmu_ecmdq __percpu *ecmdq;
> +
> +       if (num_possible_cpus() <= smmu->nr_ecmdq) {

Does the nr_ecmdq always physically match with the number of CPUs?
I saw the spec saying "up to 256 pages", but not sure if they are
always physically present, even if CPU number is smaller i.e. some
of them would be unassigned/wasted.

> +               ecmdq = devm_alloc_percpu(smmu->dev, *ecmdq);
> +               if (!ecmdq)
> +                       return -ENOMEM;
> +
> +               for_each_possible_cpu(cpu)
> +                       *per_cpu_ptr(smmu->ecmdqs, cpu) = per_cpu_ptr(ecmdq, cpu);
> +
> +               /* A core requires at most one ECMDQ */
> +               smmu->nr_ecmdq = num_possible_cpus();
> +
> +               return 0;
> +       }
> +
> +       return -ENOSPC;

This ENOSPC is a software limitation, isn't it? How about using
"smp_processor_id() % smmu->nr_ecmdq" to select a queue?

> +       shift_increment = order_base_2(num_possible_cpus() / smmu->nr_ecmdq);
> +
> +       offset = 0;
> +       for_each_possible_cpu(cpu) {
> +               struct arm_smmu_ecmdq *ecmdq;
> +               struct arm_smmu_queue *q;
> +
> +               ecmdq = *per_cpu_ptr(smmu->ecmdqs, cpu);
> +               ecmdq->base = cp_base + offset;
> +
> +               q = &ecmdq->cmdq.q;
> +
> +               q->llq.max_n_shift = ECMDQ_MAX_SZ_SHIFT + shift_increment;
> +               ret = arm_smmu_init_one_queue(smmu, q, ecmdq->base, ARM_SMMU_ECMDQ_PROD,
> +                               ARM_SMMU_ECMDQ_CONS, CMDQ_ENT_DWORDS, "ecmdq");

Not getting why max_n_shift increases by shift_increment. Mind
elaborating?

Thanks
Nicolin