From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6CFCEE49AB for ; Mon, 21 Aug 2023 09:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234315AbjHUJZa (ORCPT ); Mon, 21 Aug 2023 05:25:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbjHUJZ1 (ORCPT ); Mon, 21 Aug 2023 05:25:27 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62878C4; Mon, 21 Aug 2023 02:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692609926; x=1724145926; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=kLAaEII6sdvBluC/Z9sMXU4h15+uEOKpVCPxM/TNG74=; b=IWJfVisfEGzZosB8jMHaYzWwheO2O7wEUsnIlYSnAVlAZsJIo1sUVvpw CQ9M25N3WuOwUd3TO3FXdDmXIu8wfq9BuMpvrxcoXau7LM1C8tA2wdt01 mLli8tcFW9M1NVWmx+6oQDC04qhffjl8Db5ynz6AkEgeEABa0DCVcgqL0 8V6JiPUHrgBfbm+yJTRF5Fc38Oy2UUgoUsHANFgVACkyCl29SviQGqHpN +tW97U2yY1iYiOZUJdAO3z/ElwB11yCZv6tHN00tP0HEHNd34VhJxvtWz VrfmfDjSm50ZsMWo+DbDsJKVR+OfYMsGgLDKsAlK6L0LId8ugg3qwpmYp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="370976402" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="370976402" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 02:25:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="879451781" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga001.fm.intel.com with ESMTP; 21 Aug 2023 02:25:19 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1qY19s-007ZgT-2b; Mon, 21 Aug 2023 12:25:12 +0300 Date: Mon, 21 Aug 2023 12:25:12 +0300 From: Andy Shevchenko To: Marcus Folkesson Cc: Kent Gustavsson , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Cosmin Tanislav , Arnd Bergmann , ChiYuan Huang , Haibo Chen , Ramona Bolboaca , Ibrahim Tilki , ChiaEn Wu , William Breathitt Gray , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 6/6] iio: adc: mcp3911: add support for the whole MCP39xx family Message-ID: References: <20230820102610.755188-1-marcus.folkesson@gmail.com> <20230820102610.755188-7-marcus.folkesson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230820102610.755188-7-marcus.folkesson@gmail.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Aug 20, 2023 at 12:26:10PM +0200, Marcus Folkesson wrote: > Microchip does have many similar chips, add support for those. > > The new supported chips are: > - microchip,mcp3910 > - microchip,mcp3912 > - microchip,mcp3913 > - microchip,mcp3914 > - microchip,mcp3918 > - microchip,mcp3919 A few really minor things, after addressing them Reviewed-by: Andy Shevchenko Thank you for this journey! ... > +static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) > +{ > + unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; unsigned int value = enable ? mask : 0; > + > + if (enable) > + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, mask, 3); > + else > + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, 0, 3); return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); > +} ... > +static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) > +{ > + unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; > + > + if (enable) > + return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, mask, 2); > + else > + return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, 0, 2); > +} Ditto. ... > +static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) > +{ > + int ret, osr; unsigned int osr; > + > + ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); > + if (ret) > + return ret; > + > + osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); > + *val = 32 << osr; > + return 0; > +} ... > +static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) > +{ > + int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); Ditto. > + unsigned int mask = MCP3910_CONFIG0_OSR; > + > + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); > +} ... > +static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) > +{ > + int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); Ditto. > + unsigned int mask = MCP3911_CONFIG_OSR; > + > + return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); > +} > + > +static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) > +{ > + int ret, osr; > + > + ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); > + if (ret) > + return ret; > + > + osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); > + *val = 32 << osr; > + return ret; > +} -- With Best Regards, Andy Shevchenko