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Tue, 22 Aug 2023 09:32:25 -0700 Date: Tue, 22 Aug 2023 09:32:24 -0700 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , Subject: Re: [PATCH 3/3] iommu/arm-smmu-v3: Add a max_tlbi_ops for __arm_smmu_tlb_inv_range() Message-ID: References: <3ba332e141102d31b756326cdc4078cac1f5ab1c.1692693557.git.nicolinc@nvidia.com> <3f630d3d-c59a-f454-14db-2bf9b8e76877@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <3f630d3d-c59a-f454-14db-2bf9b8e76877@arm.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|DM4PR12MB5327:EE_ X-MS-Office365-Filtering-Correlation-Id: d54a6c3d-e48c-4d70-a7df-08dba32d677a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UHqcGallw0OE6wwbhR+q1WBNhLX6AjMhja/biGGS8N2DRu5ur1up4aAMfXl50x+EiapDC/yENyC5nv/U6wCOSdPJtvMV7v0iqas9jehculJfpGiugQuF6upkzLx2BfTBxGNUCYEaSd1Zom/EdoQO76K1ckQLa/7Qk6fDUcU8GLHzdlq9D+oDnEfqMNk1yLvnkPK88yuNgZ3ddcwUKqUhwo5R+eAnxKQDyc84GoaPQAn/b21In/3kZFwIVwSyGzU2N+3IuIhoknkP1TBWq4CutCulu8QSCtgaBmXnjBN1SpeWAjS3i6UB0wHiSwSoaz8XSOnKfxczUi+swyT/uWJiavr1PbrqMcPqRyWiX4bsObUyh2MwG2rNdOA1Y4mL5l/0moPs8EgOEtJFCRPRFJhlBzv4DHZUKtOulWkLDKrRnP9VcWQpI8Yj3bGc6e1+l+JZFWQSQQHzHawLe9LySEZJ8uXnpzRlkjDsufg/03djGu1LCPkL6FpbLbi88IQRH64o482Ti+FutQ1gNmOocsWbqfVgBjQ45D8fVcSwFDL/LNyxOq/LPvsotWLKTE1GQMx0ls9/z13TpqVRcppMhe/G10gQ2rEpMiJICryavn5z3g3ir7o92v+PpPvsXLPnor1JgH6lYJnRWlvjpIWgmIgkQ7RKRr0P8WFIsaiM20ZX9m/nj+8D2AmUUurVvZi2P5QvuQ0Zuvdvxj6e6qxUXHuQd0nUsqMkRZX5O580Vs0lb2ZBktbR4IM/CNBKtH3+3smk X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(396003)(376002)(82310400011)(451199024)(186009)(1800799009)(36840700001)(40470700004)(46966006)(2906002)(36860700001)(40480700001)(336012)(5660300002)(426003)(26005)(86362001)(47076005)(8676002)(8936002)(4326008)(70206006)(316002)(70586007)(54906003)(6916009)(9686003)(478600001)(82740400003)(356005)(55016003)(40460700003)(41300700001)(33716001)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 16:32:40.6910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d54a6c3d-e48c-4d70-a7df-08dba32d677a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5327 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 22, 2023 at 10:30:35AM +0100, Robin Murphy wrote: > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index d6c647e1eb01..3f0db30932bd 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -1897,7 +1897,14 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, > > if (!size) > > return; > > > > - if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { > > + if (!(smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { > > + /* > > + * When the size reaches a threshold, replace per-granule TLBI > > + * commands with one single per-asid or per-vmid TLBI command. > > + */ > > + if (size >= granule * smmu_domain->max_tlbi_ops) > > + return arm_smmu_tlb_inv_domain(smmu_domain); > > This looks like it's at the wrong level - we should have figured this > out before we got as far as low-level command-building. I'd have thought > it would be a case of short-circuiting directly from > arm_smmu_tlb_inv_range_domain() to arm_smmu_tlb_inv_context(). OK, I could do that. We would have copies of this same routine though. Also, the shortcut applies to !ARM_SMMU_FEAT_RANGE_INV cases only, so this function feels convenient to me. > > + } else { > > /* Get the leaf page size */ > > tg = __ffs(smmu_domain->domain.pgsize_bitmap); > > > > @@ -2258,6 +2265,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, > > } > > > > smmu_domain->pgtbl_ops = pgtbl_ops; > > + smmu_domain->max_tlbi_ops = pgtbl_cfg.nents_per_pgtable; > > And now we're carrying *three* copies of the same information around > everywhere? Honestly, just pull cfg->bits_per_level out of the > io_pgtable_ops at the point where you need it, like the pagetable code > itself manages to do perfectly happily. Wrap it in an io-pgtable helper > if you think that's cleaner. OK. I overlooked io_pgtable_ops_to_pgtable. Will do that. Thanks Nic