From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36305EE49A3 for ; Wed, 23 Aug 2023 14:31:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236440AbjHWOb7 (ORCPT ); Wed, 23 Aug 2023 10:31:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236170AbjHWOb6 (ORCPT ); Wed, 23 Aug 2023 10:31:58 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94C43E63 for ; Wed, 23 Aug 2023 07:31:56 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-26b752bc74fso6048738a91.2 for ; Wed, 23 Aug 2023 07:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692801116; x=1693405916; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=p+7iLveG+eJzHBFrfOKuJ5YG6FqnmCVegyIJkjx3CJs=; b=LzhZHLtB03/JJ1EFMYkoId7U63M6kz0rkZQdYP+DWvlThHHu5yYTmURkn+QTm93znp aDmlh3jz/Z9a3dG9h7rQfpUWUDhMW/Me62S5jR/KVyHvk9sLCeI97HayzwHA4gHzgQDN JKLH4SdNd2wo4dgiAf+TF2u4WIhjZ/xcMIbsPoRk5L3INLBE4eZt8mtQR3+ePM3qrgva aMFnwJawtJQ7LQACF6LIeqPzftsTWoWcoVwiChA/qjkVeMf98TKJ9urswuYEhAVFejO/ FTdXmJezgzkc7mtO6slkhV1UEvepS6MvxgKg+fzpNbIwgfE0FUeh2Cjg1PbppcsOcBQ7 irnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692801116; x=1693405916; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=p+7iLveG+eJzHBFrfOKuJ5YG6FqnmCVegyIJkjx3CJs=; b=STewuyVCQjUUy9+pcSVIoUAcl2ymA9c4gJ6GFrGpo1kZEu2mB07HF6MRCkmcSX3ULA BKSzVrf1K65mTzxgbF3PRQSpNAojcMD7bBChDs5UrWGZd/b2jyv0p4bS/Dr2jcoKDD9U 8OIHEYDhDxJMbFNT6Rspec43yrHbOjwITBjqZPGs0Gs5FdCIl6T/REIJ4356l9XERkiM M8I2Ch69feJKYKsdZV+SsnU2A2uZwmqsgBWRqrn4UYV83cAu3Ye9JZ1gM+uuO8BGMs0y t1zluiFN7EhbAgOYq2zulgBkFNylZ+VQRDat7KZwXY4iu5niO7mTlOEUe3GYtRsp/i5A oYxg== X-Gm-Message-State: AOJu0YxlV8mTnnre61O7WWGvB53jmSjIUlU8BrsmIg20WdjJphs9feM2 DT4LqM40Pdj8WLAZ/aEyOgh6zQwH04U= X-Google-Smtp-Source: AGHT+IGtI7MXslrycISJQNQJ0AoAcyzbEKDIHnO0byuO9FAEJ+E63W5Ojv9JmpsztfJ4GL1dF8FIqVWO81w= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90b:30cb:b0:268:1be1:b835 with SMTP id hi11-20020a17090b30cb00b002681be1b835mr2918260pjb.2.1692801116013; Wed, 23 Aug 2023 07:31:56 -0700 (PDT) Date: Wed, 23 Aug 2023 14:31:54 +0000 In-Reply-To: <498ee0c4-4736-68a7-7cbf-12e54f6a0d22@intel.com> Mime-Version: 1.0 References: <1692588392-58155-1-git-send-email-hao.xiang@linux.alibaba.com> <6d10dcf7-7912-25a2-8d8e-ef7d71a4ce83@linux.alibaba.com> <33f0e9bb-da79-6f32-f1c3-816eb37daea6@linux.alibaba.com> <498ee0c4-4736-68a7-7cbf-12e54f6a0d22@intel.com> Message-ID: Subject: Re: [PATCH] kvm: x86: emulate MSR_PLATFORM_INFO msr bits From: Sean Christopherson To: Xiaoyao Li Cc: Hao Xiang , Chao Gao , kvm@vger.kernel.org, shannon.zhao@linux.alibaba.com, pbonzini@redhat.com, linux-kernel@vger.kernel.org, Aaron Lewis Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 23, 2023, Xiaoyao Li wrote: > On 8/22/2023 12:11 AM, Sean Christopherson wrote: > > > Set these msr bits (needed by turbostat on intel platform) in KVM by > > > default. Of cource, QEMU can also set MSR value by need. It does not > > > conflict. > >=20 > > It doesn't conflict per se, but it's still problematic. By stuffing a = default > > value, KVM _forces_ userspace to override the MSR to align with the top= ology and > > CPUID defined by userspace. >=20 > I don't understand how this MSR is related to topology and CPUID? Heh, looked at the SDM to double check myself, and the first hit when searc= hing for MSR_PLATFORM_INFO says: When TSC scaling is enabled for a guest using Intel PT, the VMM should en= sure that the value of Maximum Non-Turbo Ratio[15:8] in MSR_PLATFORM_INFO (MSR= 0CEH) and the TSC/=E2=80=9Dcore crystal clock=E2=80=9D ratio (EBX/EAX) in CPUID= leaf 15H are set in a manner consistent with the resulting TSC rate that will be visible to t= he VM. As Chao pointed out, the MSR is technically per package, so a weird setup c= ould have sockets with different frequencies, or enumerate a virtual topology to= the guest with such a configuration. I doubt/hope no one actually does somethi= ng like that, but it's theoretically possible, and one of the many reasons why= KVM needs to stay out of the way and let userspace define the vCPU model. > > And if userspace uses KVM's "default" CPUID, or lack thereof, using the > > underlying values from hardware are all but guaranteed to be wrong. >=20 > Could you please elaborate? I guess an empty CPUID would probably be ok? If there's no CPUID.0x15, it = can't be wrong. It's largely a moot point though, I highly doubt anyone runs a "= real" VM without populating _something_ in guest CPUID.