Re: [PATCH v17 14/14] arm64: dts: mediatek: mt8195: Add SCP 2nd core

Mathieu Poirier
2023-09-04T17:48:33Z

Hey Matthias - will you pick up this one or should I get it through
the remoteproc tree?

On Fri, 1 Sept 2023 at 02:10, Tinghan Shen <tinghan.shen@mediatek.com> wrote:
>
> Rewrite the MT8195 SCP device node as a cluster and
> add the SCP 2nd core in it.
>
> Since the SCP device node is changed to multi-core structure,
> enable SCP cluster to enable probing SCP core 0.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++-
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 34 ++++++++++++++-----
> 2 files changed, 30 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 37a3e9de90ff..4584077d3a4c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -991,7 +991,11 @@
> interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> -&scp {
> +&scp_cluster {
> + status = "okay";
> +};
> +
> +&scp_c0 {
> status = "okay";
>
> firmware-name = "mediatek/mt8195/scp.img";
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 48b72b3645e1..7809118f74fb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -922,14 +922,30 @@
> clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
> };
>
> - scp: scp@10500000 {
> - compatible = "mediatek,mt8195-scp";
> - reg = <0 0x10500000 0 0x100000>,
> - <0 0x10720000 0 0xe0000>,
> - <0 0x10700000 0 0x8000>;
> - reg-names = "sram", "cfg", "l1tcm";
> - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
> + scp_cluster: scp@10500000 {
> + compatible = "mediatek,mt8195-scp-dual";
> + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>;
> + reg-names = "cfg", "l1tcm";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x10500000 0x100000>;
> status = "disabled";
> +
> + scp_c0: scp@0 {
> + compatible = "mediatek,scp-core";
> + reg = <0x0 0xa0000>;
> + reg-names = "sram";
> + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
> + status = "disabled";
> + };
> +
> + scp_c1: scp@a0000 {
> + compatible = "mediatek,scp-core";
> + reg = <0xa0000 0x20000>;
> + reg-names = "sram";
> + interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
> + status = "disabled";
> + };
> };
>
> scp_adsp: clock-controller@10720000 {
> @@ -2374,7 +2390,7 @@
>
> video-codec@18000000 {
> compatible = "mediatek,mt8195-vcodec-dec";
> - mediatek,scp = <&scp>;
> + mediatek,scp = <&scp_c0>;
> iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -2540,7 +2556,7 @@
> <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
> <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
> interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
> - mediatek,scp = <&scp>;
> + mediatek,scp = <&scp_c0>;
> clocks = <&vencsys CLK_VENC_VENC>;
> clock-names = "venc_sel";
> assigned-clocks = <&topckgen CLK_TOP_VENC>;
> --
> 2.18.0
>